MT41J256M8HX-15E IT:D Micron Technology Inc, MT41J256M8HX-15E IT:D Datasheet - Page 14

• Manufacturer Part Number: MT41J256M8HX-15E IT:D
• Description: MICMT41J256M8HX-15E_IT:D 2GB DDR3 SDRAM
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J256M8HX-15E IT:D

• Organization: 256Mx8
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: -40C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 165mA
• Pin Count: 78
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

Functional Block Diagrams
Figure 3: 512 Meg x 4 Functional Block Diagram
RZQ
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
V
SSQ
A[14:0]
BA[2:0]
ZQ
CK, CK#
RESET#
RAS#
CAS#
WE#
ODT
CKE
A12
CS#
18
Address
register
Mode registers
Control
logic
18
15
counter
Refresh
ZQCL, ZQCS
11
3
BC4 (burst chop)
OTF
DDR3 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally
configured as an 8-bank DRAM.
15
address
3
Row-
MUX
Column-
counter/
control
address
15
Bank
logic
latch
ZQ CAL
decoder
address
Bank 0
row-
latch
and
Bank 1
Bank 2
8
3
Bank 3
Bank 4
32,768
Bank 5
Bank 6
Columns 0, 1, and 2
Bank 7
To pullup/pulldown
(32,768 x 256 x 32)
Sense amplifiers
DM mask logic
I/O gating
Column
decoder
networks
memory
Bank 0
(x32)
8,192
array
256
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
14
Bank 7
DM
32
BC4
OTF
Micron Technology, Inc. reserves the right to change products or specifications without notice.
32
32
Columns 0, 1, and 2
interface
READ
CK,CK#
FIFO
data
MUX
and
Data
2Gb: x4, x8, x16 DDR3 SDRAM
Data
4
4
lower nibble for BC4)
(select upper or
Functional Block Diagrams
Column 2
WRITE
drivers
input
and
logic
control
ODT
CK,CK#
drivers
READ
DLL
BC4
© 2006 Micron Technology, Inc. All rights reserved.
DQS, DQS#
sw1
sw1
sw1
DQ[3:0]
R
V
V
R
V
R
TT,nom
DDQ
TT,nom
DDQ
DDQ
TT,nom
/2
/2
/2
sw2
R
R
sw2
sw2
R
TT(WR)
TT(WR)
TT(WR)
(1, 2)
(1 . . . 4)
DQ[3:0]
DQS, DQS#
DM