EP3C5F256C8N Altera, EP3C5F256C8N Datasheet - Page 103
EP3C5F256C8N
Manufacturer Part Number
EP3C5F256C8N
Description
IC CYCLONE III FPGA 5K 256-FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
Specifications of EP3C5F256C8N
Number Of Logic Elements/cells
5136
Number Of Labs/clbs
321
Total Ram Bits
423936
Number Of I /o
182
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-FBGA
No. Of Logic Blocks
321
Family Type
Cyclone III
No. Of I/o's
182
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2423
EP3C5F256C8N
EP3C5F256C8N
Available stocks
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Manufacturer
Quantity
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Part Number:
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Manufacturer:
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Quantity:
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Part Number:
EP3C5F256C8N
Manufacturer:
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Chapter 6: I/O Features in the Cyclone III Device Family
I/O Element Features
© December 2009
f
f
1
Altera Corporation
For more information about programmable current strength, refer to the
Editor
Table 6–1
These programmable current strength settings are a valuable tool in helping decrease
the effects of simultaneously switching outputs (SSO) in conjunction with reducing
system noise. The supported settings ensure that the device driver meets the
specifications for IOH and IOL of the corresponding I/O standard.
When you use programmable current strength, on-chip series termination is not
available.
Table 6–1. Programmable Current Strength
For information about how to interface the Cyclone III device family with 3.3-, 3.0-, or
2.5-V systems, refer to the guidelines provided in
Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O
1.2-V LVCMOS
1.5-V LVCMOS
1.8-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
3.0-V LVCMOS
3.0-V LVTTL
3.3-V LVCMOS
3.3-V LVTTL
HSTL-12 Class I
HSTL-12 Class II
HSTL-15 Class I
HSTL-15 Class II
HSTL-18 Class I
HSTL-18 Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
SSTL-2 Class II
BLVDS
Notes to
(1) The default setting in the Quartus II software is 50-Ω OCT without calibration for all non-voltage reference and
(2) The default current setting in the Quartus II software is highlighted in bold italic for 3.3-V LVTTL and 3.3-V LVCMOS
HSTL/SSTL Class I I/O standards. The default setting is 25-Ω OCT without calibration for HSTL/SSTL Class II I/O
standards.
I/O standards.
chapter in volume 2 of the Quartus II Handbook.
Table
I/O Standard
lists the possible settings for I/O standards with current strength control.
(2)
6–1:
(2)
Top and Bottom I/O Pins
2, 4, 6, 8, 10, 12,16
2, 4, 6, 8, 10, 12,16
2, 4, 6, 8, 10,12
4, 8, 12,16
4, 8, 12,16
4, 8, 12,16
8, 10, 12
8, 10, 12
8, 10, 12
8, 12, 16
8, 10,12
(Note 1)
12, 16
8, 12
4, 8
14
16
16
16
I
2
O H
/I
OL
Systems.
Current Strength Setting (mA)
AN 447: Interfacing Cyclone III
Cyclone III Device Handbook, Volume 1
Left and Right I/O Pins
2, 4, 6, 8, 10, 12,16
2, 4, 6, 8, 10, 12,16
2, 4, 6, 8,10
4, 8, 12,16
4, 8, 12,16
4, 8, 12,16
8, 10, 12
8, 10, 12
8, 10, 12
8, 12, 16
12, 16
8, 10
8, 12
4, 8
—
16
16
16
2
Assignment
6–3
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