EP3C5F256C8N Altera, EP3C5F256C8N Datasheet - Page 198
EP3C5F256C8N
Manufacturer Part Number
EP3C5F256C8N
Description
IC CYCLONE III FPGA 5K 256-FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
Specifications of EP3C5F256C8N
Number Of Logic Elements/cells
5136
Number Of Labs/clbs
321
Total Ram Bits
423936
Number Of I /o
182
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-FBGA
No. Of Logic Blocks
321
Family Type
Cyclone III
No. Of I/o's
182
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2423
EP3C5F256C8N
EP3C5F256C8N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C5F256C8N
Manufacturer:
ALTERA
Quantity:
853
Part Number:
EP3C5F256C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- EP3C5F256C8N PDF datasheet
- EP3C5F256C8N PDF datasheet #2
- EP3C5F256C8N PDF datasheet #3
- EP3C5F256C8N PDF datasheet #4
- EP3C5F256C8N PDF datasheet #5
- EP3C10M164C8N PDF datasheet #6
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9–38
Cyclone III Device Handbook, Volume 1
Figure 9–16
family is receiving the same configuration data.
Figure 9–16. Multi-Device PS Configuration When Both Devices Receive the Same Data
Notes to
(1) The pull-up resistor must be connected to a supply that provides an acceptable input signal for all devices in the
(2) The nCEO pins of both devices are left unconnected or used as user I/O pins when configuring the same
(3) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0],
(4) All I/O inputs must maintain a maximum AC voltage of 4.1 V. DATA[0] and DCLK must fit the maximum overshoot
(MAX II Device or
Microprocessor)
External Host
chain. V
configuration data into multiple devices.
refer to
equation outlined in
ADDR
Figure
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Memory
Table 9–7 on page
CC
DATA[0]
must be high enough to meet the V
shows a multi-device PS configuration when both Cyclone III device
9–16:
10 k
V
“Configuration and JTAG Pin I/O Requirements” on page
CCIO
9–11. Connect the MSEL pins directly to V
(1) V
10 k
CCIO
GND
(1)
Buffers (4)
Cyclone III Device Family
IH
CONF_DONE
nSTATUS
nCE
DATA[0] (4)
nCONFIG
DCLK (4)
specification of the I/O on the device and the external host.
MSEL[3..0]
nCEO
(3)
N.C. (2)
CCA
or ground.
© December 2009 Altera Corporation
9–7.
GND
Cyclone III Device Family
CONF_DONE
nSTATUS
nCE
DATA[0] (4)
nCONFIG
DCLK (4)
Configuration Features
MSEL[3..0]
nCEO
N.C. (2)
(3)
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