EP3C5F256C8N Altera, EP3C5F256C8N Datasheet - Page 255

• Manufacturer Part Number: EP3C5F256C8N
• Description: IC CYCLONE III FPGA 5K 256-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C5F256C8N

• Number Of Logic Elements/cells: 5136
• Number Of Labs/clbs: 321
• Total Ram Bits: 423936
• Number Of I /o: 182
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• No. Of Logic Blocks: 321
• Family Type: Cyclone III
• No. Of I/o's: 182
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2423; EP3C5F256C8N

Error Detection Fundamentals
© December 2009
CIII51013-2.2
Altera Corporation
Dedicated circuitry built into the Cyclone
Cyclone III LS devices) consists of a cyclical redundancy check (CRC) error detection
feature that can optionally check for a single-event upset (SEU) continuously and
automatically.
In critical applications used in the fields of avionics, telecommunications, system
control, medical, and military applications, it is important to be able to:
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This chapter describes how to activate and use the error detection CRC feature in user
mode and describes how to recover from configuration errors caused by CRC error.
Using the CRC error detection feature for Cyclone III device family does not impact
fitting or performance.
This chapter contains the following sections:
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Error detection determines if the data received through an input device is corrupted
during transmission. In validating the data, the transmitter uses a function to
calculate a checksum value for the data and appends the checksum to the original
data frame. The receiver uses the same calculation methodology to generate a
checksum for the received data frame and compares the received checksum to the
transmitted checksum. If the two checksum values are equal, the received data frame
is correct and no data corruption has occurred during transmission or storage.
The error detection CRC feature in Cyclone III device family puts theory into practice.
In user mode, the error detection CRC feature in Cyclone III device family ensures the
integrity of the configuration data.
Confirm the accuracy of the configuration data stored in an FPGA device
Alert the system to an occurrence of a configuration error
“Error Detection Fundamentals” on page 11–1
“Configuration Error Detection” on page 11–2
“User Mode Error Detection” on page 11–2
“Automated SEU Detection” on page 11–3
“CRC_ERROR Pin” on page 11–3
“Table 11–2 lists the CRC_ERROR pin.” on page 11–3
“Error Detection Block” on page 11–4
“Error Detection Timing” on page 11–5
“Software Support” on page 11–6
“Recovering from CRC Errors” on page 11–10
11. SEU Mitigation in the Cyclone III
®
III device family (Cyclone III and
Cyclone III Device Handbook, Volume 1
Device Family