EP3C5F256C8N Altera, EP3C5F256C8N Datasheet - Page 53

• Manufacturer Part Number: EP3C5F256C8N
• Description: IC CYCLONE III FPGA 5K 256-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C5F256C8N

• Number Of Logic Elements/cells: 5136
• Number Of Labs/clbs: 321
• Total Ram Bits: 423936
• Number Of I /o: 182
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• No. Of Logic Blocks: 321
• Family Type: Cyclone III
• No. Of I/o's: 182
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2423; EP3C5F256C8N

Chapter 3: Memory Blocks in the Cyclone III Device Family
Design Considerations
© December 2009
Altera Corporation
Same-Port Read-During-Write Mode
This mode applies to a single-port RAM or the same port of a true dual-port RAM. In
the same port read-during-write mode, there are two output choices: New Data mode
(or flow-through) and Old Data mode. In New Data mode, new data is available on
the rising edge of the same clock cycle on which it was written. In Old Data mode, the
RAM outputs reflect the old data at that address before the write operation proceeds.
When using New Data mode together with byteena, you can control the output of
the RAM. When byteena is high, the data written into the memory passes to the
output (flow-through). When byteena is low, the masked-off data is not written into
the memory and the old data in the memory appears on the outputs. Therefore, the
output can be a combination of new and old data determined by byteena.
Figure 3–15
read-during-write behavior with both New Data and Old Data modes, respectively.
Figure 3–15. Same Port Read-During Write: New Data Mode
Figure 3–16. Same Port Read-During-Write: Old Data Mode
q_a (asynch)
q_a (asynch)
address_a
address_a
wren_a
wren_a
data_a
rden_a
rden_a
data_a
clk_a
clk_a
and
Figure 3–16
A
A
a0(old data)
show sample functional waveforms of same port
A
a0
a0
B
B
A
B
C
C
B
C
D
D
a1(old data)
D
Cyclone III Device Handbook, Volume 1
a1
a1
E
E
D
E
F
F
E
F
3–17