EP3C5F256C8N Altera, EP3C5F256C8N Datasheet - Page 343

• Manufacturer Part Number: EP3C5F256C8N
• Description: IC CYCLONE III FPGA 5K 256-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C5F256C8N

• Number Of Logic Elements/cells: 5136
• Number Of Labs/clbs: 321
• Total Ram Bits: 423936
• Number Of I /o: 182
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• No. Of Logic Blocks: 321
• Family Type: Cyclone III
• No. Of I/o's: 182
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2423; EP3C5F256C8N

Chapter 2: Cyclone III LS Device Data Sheet
I/O Timing
Table 2–38. Cyclone III LS Devices IOE Programmable Delay on Row Pins
I/O Timing
© December 2009
Input delay from the pin to the
internal cells
Input delay from the pin to the
input register
Delay from the output register to
the output pin
Input delay from the
dual-purpose clock pin to the
fan-out destinations
Notes to
(1) The incremental values for the settings are generally linear. For the exact values of each setting, use the latest version of the Quartus II software.
(2) The minimum and maximum offset timing numbers refer to the 0 setting available in the Quartus II software.
Table
Parameter
f
f
2–38:
Altera Corporation
DirectDrive technology and MultiTrack interconnect ensure predictable performance,
accurate simulation, and accurate timing analysis across all Cyclone III LS device
densities and speed grades.
Use the following methods to determine I/O timing:
■
■
Excel-based I/O timing provides pin timing performance for each device density and
speed grade. The data is typically used before designing the FPGA to get a timing
budget estimation as part of the link timing analysis. The Quartus II Timing Analyzer
provides a more accurate and precise I/O timing data based on the specifics of the
design after place-and-route is complete.
For more information about the Excel-based I/O timing spreadsheet, refer to the
Cyclone III Devices
All specifications are representative of worst-case supply voltage and junction
temperature conditions. Altera characterizes timing delays at the worst-case process,
minimum voltage, and maximum temperature for input register setup time (t
hold time (t
For more information about timing delay from the FPGA output to the receiving
device for system-timing analysis, refer to
for Altera Devices.
The Excel-based I/O timing
The Quartus II Timing Analyzer
Pad to I/O
dataout to core
Pad to I/O input
register
I/O output
register to pad
Pad to global
clock network
H
Paths Affected
).
Literature page on the Altera website.
Number
setting
12
of
7
8
2
Offset
Min
0
0
0
0
AN 366: Understanding I/O Output Timing
(Note
1.209 1.314 2.352 2.514 2.432
1.207 1.312 2.402 2.558 2.447
0.549 0.595 1.135 1.226 1.151
0.52
Fast Corner
I7
1),
(2)
0.54
C7
Cyclone III Device Handbook, Volume 2
Max Offset
1.052
C7
Slow Corner
1.16
C8
1.061
I7
SU
) and
Unit
ns
ns
ns
ns
2–25