EP3C5F256C8N Altera, EP3C5F256C8N Datasheet - Page 76
EP3C5F256C8N
Manufacturer Part Number
EP3C5F256C8N
Description
IC CYCLONE III FPGA 5K 256-FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
Specifications of EP3C5F256C8N
Number Of Logic Elements/cells
5136
Number Of Labs/clbs
321
Total Ram Bits
423936
Number Of I /o
182
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-FBGA
No. Of Logic Blocks
321
Family Type
Cyclone III
No. Of I/o's
182
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2423
EP3C5F256C8N
EP3C5F256C8N
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
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Manufacturer:
ALTERA
Quantity:
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Part Number:
EP3C5F256C8N
Manufacturer:
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5–12
Clock Feedback Modes
Source-Synchronous Mode
Cyclone III Device Handbook, Volume 1
1
Cyclone III device family PLLs support up to four different clock feedback modes.
Each mode allows clock multiplication and division, phase shifting, and
programmable duty cycle.
Input and output delays are fully compensated by the PLL only when you are using
the dedicated clock input pins associated with a given PLL as the clock sources. For
example, when using PLL1 in normal mode, the clock delays from the input pin to the
PLL and the PLL clock output-to-destination register are fully compensated, provided
that the clock input pin is one of the following four pins:
■
■
■
■
When driving the PLL using the GCLK network, the input and output delays may not
be fully compensated in the Quartus II software.
If the data and clock arrive at the same time at the input pins, the phase relationship
between the data and clock remains the same at the data and clock ports of any I/O
element input register.
Figure 5–8
mode for source-synchronous data transfers. Data and clock signals at the I/O
element experience similar buffer delays as long as the same I/O standard is used.
Figure 5–8. Phase Relationship Between Data and Clock in Source-Synchronous Mode
Source-synchronous mode compensates for delay of the clock network used,
including any difference in the delay between the following two paths:
■
■
CLK0
CLK1
CLK2
CLK3
Data pin to I/O element register input
Clock input pin to the PLL phase-frequency detector (PFD) input
shows an example waveform of the data and clock in this mode. Use this
clock at input pin
Clock at register
Data at register
PLL reference
Data pin
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
© December 2009 Altera Corporation
Clock Feedback Modes
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