EP3C5F256C8N Altera, EP3C5F256C8N Datasheet - Page 145
EP3C5F256C8N
Manufacturer Part Number
EP3C5F256C8N
Description
IC CYCLONE III FPGA 5K 256-FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
Specifications of EP3C5F256C8N
Number Of Logic Elements/cells
5136
Number Of Labs/clbs
321
Total Ram Bits
423936
Number Of I /o
182
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-FBGA
No. Of Logic Blocks
321
Family Type
Cyclone III
No. Of I/o's
182
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2423
EP3C5F256C8N
EP3C5F256C8N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C5F256C8N
Manufacturer:
ALTERA
Quantity:
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Part Number:
EP3C5F256C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
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- EP3C5F256C8N PDF datasheet
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Figure 8–1. Cyclone III Device Family External Memory Data Path
Note to
(1) All clocks shown here are global clocks.
© January 2010 Altera Corporation
CIII51009-2.3
Figure
8–1:
f
PLL
1
-90° Shifted Clock
OE
In addition to an abundant supply of on-chip memory, Cyclone
(Cyclone III and Cyclone III LS devices) can easily interface to a broad range of
external memory, including DDR2 SDRAM, DDR SDRAM, and QDRII SRAM.
External memory devices are an important system component of a wide range of
image processing, storage, communications, and general embedded applications.
Altera
interfaces using the Altera ALTMEMPHY megafunction. You can implement the
controller function using the Altera DDR2 or DDR SDRAM memory controllers,
third-party controllers, or a custom controller for unique application needs.
Cyclone III device family supports QDR II interfaces electrically, but Altera does not
supply controller or physical layer (PHY) megafunctions for QDR II interfaces.
This chapter includes a description of the hardware interfaces for external memory
interfaces available in Cyclone III device family.
This chapter contains the following sections:
■
■
For more information about external memory system performance specifications,
board design guidelines, timing analysis, simulation, and debugging information,
refer to
Figure 8–1
in Cyclone III device family.
Register
System Clock
IOE
Register
“Cyclone III Device Family Memory Interfaces Pin Support” on page 8–2
“Cyclone III Device Family Memory Interfaces Features” on page 8–10
IOE
®
GND
V CC
recommends that you construct all DDR2 or DDR SDRAM external memory
Literature: External Memory
Capture Clock
shows the block diagram of a typical external memory interface data path
Register
Register
IOE
IOE
DQS/CQ/CQn
8. External Memory Interfaces in the
OE
Register
IOE
Register
Interfaces.
IOE
(Note 1)
DataA
DataB
Register
Register
Cyclone III Device Family
IOE
IOE
DQ
Cyclone III Device Handbook, Volume 1
Register
Register
®
LE
LE
III device family
Register
LE
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