EP3C5F256C8N Altera, EP3C5F256C8N Datasheet - Page 234

• Manufacturer Part Number: EP3C5F256C8N
• Description: IC CYCLONE III FPGA 5K 256-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C5F256C8N

• Number Of Logic Elements/cells: 5136
• Number Of Labs/clbs: 321
• Total Ram Bits: 423936
• Number Of I /o: 182
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• No. Of Logic Blocks: 321
• Family Type: Cyclone III
• No. Of I/o's: 182
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2423; EP3C5F256C8N

9–74
Key Storage
Cyclone III Device Handbook, Volume 1
f
1
1
Cyclone III LS devices support volatile key programming.
key features.
Table 9–24. Security Key Features
AES volatile key zeroization is supported in Cyclone III LS devices. The volatile key
clear and key program JTAG instructions from the device core is supported to protect
Cyclone III LS devices against tampering. You can clear and reprogram the key from
the device core whenever tampering attempt is detected by executing the
KEY_CLR_VREG and KEY_PROG_VOL JTAG instructions to clear and reprogram the
volatile key, and then reset the Cyclone III LS device by pulling the nCONFIG pin low
for at least 500 ns. When nCONFIG returns to a logic-high level and nSTATUS is
released by the Cyclone III LS device, reconfiguration begins to configure the
Cyclone III LS device with a benign or unencrypted configuration file. After
configuration is successfully completed, observe the cyclecomplete signal from
error detection block to ensure that reconfigured CRAM bits content is correct for at
least one error detection cycle. You can also observe the cyclecomplete and
crcerror signals for any unintentional CRAM bits change.
cyclecomplete is a signal that is routed from the error detection block to the core
for the purpose of every complete error detection cycle. You must include the
cycloneiiils_crcblock WYSIWYG atom in your design to use the
cyclecomplete signal. For more information about the SEU mitigation, refer to the
SEU Mitigation in Cyclone III Devices
V
other on-chip power supplies, such as V
power to the volatile register regardless of the on-chip supply condition. The nominal
voltage for this supply is 3.0 V, while its valid operating range is from 1.2 to 3.3 V. If
you do not use the volatile security key, you may connect the V
3.0-V power supply.
After power-up, wait for 200 ms (Standard POR) or 9 ms (Fast POR) before beginning
the key programming to ensure that V
As an example, BR1220 (-30°C to +80°C) and BR2477A (-40 C to +125°C) are lithium
coin-cell type batteries used for volatile key storage purposes.
Key programmability
External battery
Key programming method
Design protection
Note to
(1) Key programming is carried out using the JTAG interface.
CCBAT
is a dedicated power supply for the volatile key storage and not shared with
Table
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Volatile Key Features
9–24:
(1)
chapter.
CCBAT
CCIO
Reprogrammable and erasable
Required
On-board
Secure against copying, reverse engineering, and
tampering
is at its full rail.
or V
CC
. V
CCBAT
© December 2009 Altera Corporation
continuously supplies
Description
Table 9–24
CCBAT
to a 1.8-V, 2.5-V, or
lists the volatile
Design Security