EP3C55F484C8N Altera, EP3C55F484C8N Datasheet - Page 156

• Manufacturer Part Number: EP3C55F484C8N
• Description: IC CYCLONE III FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C55F484C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2396160
• Number Of I /o: 327
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 327
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 3491
• Family Type: Cyclone III
• No. Of I/o's: 327
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2510

8–12
DDR Output Registers
Figure 8–5. Cyclone III Device Family Dedicated Write DDIO
Cyclone III Device Handbook, Volume 1
f
-90° Shifted Clock
A dedicated write DDIO block is implemented in the DDR output and output enable
paths.
Figure 8–5
implemented in the I/O element (IOE) registers.
The two DDR output registers are located in the I/O element (IOE) block. Two serial
data streams routed through datain_l and datain_h, are fed into two registers,
output register Ao and output register Bo, respectively, on the same clock
edge. The output from output register Ao is captured on the falling edge of the
clock, while the output from output register Bo is captured on the rising edge of
the clock. The registered outputs are multiplexed by the common clock to drive the
DDR output pin at twice the data rate.
The DDR output enable path has a similar structure to the DDR output path in the
IOE block. The second output enable register provides the write preamble for the DQS
strobe in DDR external memory interfaces. This active-low output enable register
extends the high-impedance state of the pin by half a clock cycle to provide the
external memory’s DQS write preamble time specification.
For more information about Cyclone III device family IOE registers, refer to the
Cyclone III Device I/O Features
Output Enable
datain_h
datain_l
shows how Cyclone III device family dedicated write DDIO block is
Output Register A
Output Register B
Output Enable
Register A
Output Enable
Register B
Register
Register
Register
Register
chapter.
IOE
IOE
IOE
IOE
DDR Output Enable Registers
DDR Output Registers
Chapter 8: External Memory Interfaces in the Cyclone III Device Family
OE
OE
O
O
data0
data1
data1
data0
®
Cyclone III Device Family Memory Interfaces Features
© January 2010 Altera Corporation
DQ or DQS