EP3C55F484C8N Altera, EP3C55F484C8N Datasheet - Page 90

• Manufacturer Part Number: EP3C55F484C8N
• Description: IC CYCLONE III FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C55F484C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2396160
• Number Of I /o: 327
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 327
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 3491
• Family Type: Cyclone III
• No. Of I/o's: 327
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2510

5–26
Figure 5–21. PLL Reconfiguration Scan Chain
Cyclone III Device Handbook, Volume 1
configupdate
scandataout
scanclkena
scandone
scandata
scanclk
areset
1
1
The counter settings are updated synchronously to the clock frequency of the
individual counters. Therefore, not all counters update simultaneously.
To reconfigure the PLL counters, perform the following steps:
1. The scanclkena signal is asserted at least one scanclk cycle prior to shifting in
2. Serial data (scandata) is shifted into the scan chain on the second rising edge of
3. After all 144 bits have been scanned into the scan chain, the scanclkena signal is
4. The configupdate signal is asserted for one scanclk cycle to update the PLL
5. The scandone signal goes high indicating that the PLL is being reconfigured. A
6. Reset the PLL using the areset signal if you make any changes to the M, N,
7. You can repeat steps
Figure 5–21
When reconfiguring the counter clock frequency, the corresponding counter phase
shift settings cannot be reconfigured using the same interface. You can reconfigure
phase shifts in real time using the dynamic phase shift reconfiguration interface. If
you reconfigure the counter frequency, but wish to keep the same non-zero phase
shift setting (for example, 90°) on the clock output, you must reconfigure the phase
shift after reconfiguring the counter clock frequency.
Dn_old
the first bit of scandata (Dn).
scanclk.
deasserted to prevent inadvertent shifting of bits in the scan chain.
counters with the contents of the scan chain.
falling edge indicates that the PLL counters have been updated with new settings.
post-scale output C counters, or the I
Dn
shows a functional simulation of the PLL reconfiguration feature.
1
through
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
5
to reconfigure the PLL any number of times.
CP
, R, C settings.
D0_old
LSB
D0
© December 2009 Altera Corporation
Dn
PLL Reconfiguration