EP3C55F484C8N Altera, EP3C55F484C8N Datasheet - Page 177

• Manufacturer Part Number: EP3C55F484C8N
• Description: IC CYCLONE III FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C55F484C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2396160
• Number Of I /o: 327
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 327
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 3491
• Family Type: Cyclone III
• No. Of I/o's: 327
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2510

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
© December 2009
1
Altera Corporation
Multiple SRAM Object Files
Two copies of the .sof are stored in the serial configuration device. Use the first copy
to configure the master device of the Cyclone III device family and the second copy to
configure all the remaining slave devices concurrently. All slave devices must be of
the same density and package. The setup is similar to
which the master device is set up in AS mode and the slave devices are set up in PS
mode.
To configure four identical Cyclone III device family with the same .sof, you must set
up the chain similar to
pins must be set to select the AS configuration. The other three slave devices are set
up for concurrent configuration and their MSEL pins must be set to select the PS
configuration. The nCEO pin from the master device drives the nCE input pins on all
three slave devices, as well as the DATA and DCLK pins that connect in parallel to all
four devices. During the first configuration cycle, the master device reads its
configuration data from the serial configuration device while holding nCEO high.
After completing its configuration cycle, the master device drives nCE low and sends
the second copy of the configuration data to all three slave devices, configuring them
simultaneously.
The advantage of using the setup in
the master device. However, all the slave devices must be configured with the same
.sof. In this configuration method, you can either compress or uncompress the .sofs.
You can still use this method if the master and slave devices use the same .sof.
Figure
9–5. The first device is the master device and its MSEL
Figure 9–5
is that you can have a different .sof for
Figure 9–4 on page
Cyclone III Device Handbook, Volume 1
9–15, in
9–17