EP3C55F484C8N Altera, EP3C55F484C8N Datasheet - Page 215

• Manufacturer Part Number: EP3C55F484C8N
• Description: IC CYCLONE III FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C55F484C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2396160
• Number Of I /o: 327
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 327
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 3491
• Family Type: Cyclone III
• No. Of I/o's: 327
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2510

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
Figure 9–27. JTAG Configuration of Multiple Devices Using a Download Cable (1.2, 1.5, and 1.8-V V
Pins)
Notes to
(1) Connect these pull-up resistors to the V
(2) Connect the nCONFIG and MSEL[3..0] pins to support a non-JTAG configuration scheme. If you only use a JTAG configuration, connect the
(3) In the USB-Blaster and ByteBlaster II cable, this pin is connected to nCE when it is used for AS programming, otherwise it is a no connect.
(4) The nCE pin must be connected to ground or driven low for successful JTAG configuration.
(5) Power up the V
© December 2009
Pin 1
10-Pin Male Header
Download Cable
nCONFIG pin to logic high and the MSEL[3..0] pins to ground. In addition, pull DCLK and DATA[0] either high or low, whichever is
convenient on your board.
target supply voltage of 1.2 V. For the target supply voltage value, refer to the
Download Cable User
V
Figure
CCIO
(5)
10 kΩ
VIO
V
(3)
9–27:
CCIO (1)
1 kΩ
1
CC
Altera Corporation
V
of the ByteBlaster II or USB-Blaster cable with supply from V
CCIO (1)
10 kΩ
Guide.
All I/O inputs must maintain a maximum AC voltage of 4.1 V. If a non-Cyclone III
device family is cascaded in the JTAG-chain, TDO of the non-Cyclone III device family
driving into TDI of the Cyclone III device family must fit the maximum overshoot
equation outlined in
The nCE pin must be connected to GND or driven low during JTAG configuration. In
multi-device AS, AP, PS, and FPP configuration chains, the nCE pin of the first device
is connected to GND while its nCEO pin is connected to the nCE pin of the next device
in the chain. The inputs of the nCE pin of the last device come from the previous
device while its nCEO pin is left floating. In addition, the CONF_DONE and nSTATUS
signals are shared in multi-device AS, AP, PS, and FPP configuration chains to ensure
that the devices enter user mode at the same time after configuration is complete.
When the CONF_DONE and nSTATUS signals are shared among all the devices, every
device must be configured when you perform JTAG configuration.
If you only use JTAG configuration, Altera recommends that you connect the circuitry
as shown in
nSTATUS signals are isolated so that each device can enter user mode individually.
(2)
(2)
(2)
(2)
(2)
V
CCIO
10
(1)
nST A TUS
DATA[0]
DCLK
nCONFIG
MSEL[3..0]
nCEO
nCE
TDI
kΩ
TMS
(4)
Device Family
CCIO
Cyclone III
Figure 9–26
TCK
CONF_DONE
supply of the bank in which the pin resides.
TDO
“Configuration and JTAG Pin I/O Requirements” on page
V
CCIO
or
10
(1)
Figure
kΩ
(2)
(2)
(2)
(2)
(2)
V
CCIO
9–27, in which each of the CONF_DONE and
10
(1)
DATA[0]
DCLK
MSEL[3..0]
nCE
TDI
nST A TUS
nCONFIG
nCEO
kΩ
TMS
ByteBlaster II Download Cable User Guide
(4)
CCIO
Device Family
. The ByteBlaster II and USB-Blaster cables do not support a
Cyclone III
TCK
CONF_DONE
TDO
V
CCIO
10
(1)
kΩ
Cyclone III Device Handbook, Volume 1
(2)
(2)
(2)
(2)
(2)
V
CCIO
10
CCIO
(1)
nST A TUS
DATA[0]
DCLK
nCONFIG
MSEL[3..0]
nCEO
nCE
TDI
kΩ
TMS
Powering the JTAG
(4)
and the
Device Family
Cyclone III
CONF_DONE
TCK
USB-Blaster
TDO
9–7.
V
CCIO
9–55
10
(1)
kΩ