EP3C55F484C8N Altera, EP3C55F484C8N Datasheet - Page 169

• Manufacturer Part Number: EP3C55F484C8N
• Description: IC CYCLONE III FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C55F484C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2396160
• Number Of I /o: 327
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 327
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 3491
• Family Type: Cyclone III
• No. Of I/o's: 327
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2510

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
© December 2009
f
Altera Corporation
Cyclone III LS devices are accessible by limited JTAG instructions after POR. For more
information about enabling full JTAG instructions access, refer to
on page
For more information about the value of weak pull-up resistors on the I/O pins that
are on before and during configuration, refer to the
Cyclone III LS Device Data Sheet
Configuration
Configuration data is latched into the Cyclone III device family at each DCLK cycle.
However, the width of the data bus and the configuration time taken for each scheme
are different. After the device receives all the configuration data, the device releases
the open-drain CONF_DONE pin, which is pulled high by an external 10-kΩ pull-up
resistor. A low-to-high transition on the CONF_DONE pin indicates that configuration
is complete and initialization of the device can begin. The CONF_DONE pin must have
an external 10-kΩ pull-up resistor for the device to initialize.
You can begin reconfiguration by pulling the nCONFIG pin low. The nCONFIG pin
must be low for at least 500 ns. When nCONFIG is pulled low, the Cyclone III device
family is reset. The Cyclone III device family also pulls nSTATUS and CONF_DONE low
and all I/O pins are tri-stated. When nCONFIG returns to a logic-high level and
nSTATUS is released by the Cyclone III device family, reconfiguration begins.
Configuration Error
If an error occurs during configuration, the Cyclone III device family asserts the
nSTATUS signal low, indicating a data frame error, and the CONF_DONE signal stays
low. If the Auto-restart configuration after error option (available in the Quartus II
software from the General tab of the Device and Pin Options dialog box) is turned
on, the Cyclone III device family releases nSTATUS after a reset time-out period (a
maximum of 230 μs), and retries configuration. If this option is turned off, the system
must monitor nSTATUS for errors and then pulse nCONFIG low for at least 500 ns to
restart configuration.
Initialization
In Cyclone III device family, the clock source for initialization is either a 10-MHz
(typical) internal oscillator (separate from the AS internal oscillator) or an optional
CLKUSR pin. By default, the internal oscillator is the clock source for initialization. If
you use the internal oscillator, the device provides itself with enough clock cycles for a
proper initialization. When using the internal oscillator, you do not need to send
additional clock cycles from an external source to the CLKUSR pin during the
initialization stage. Additionally, you can use the CLKUSR pin as a user I/O pin.
You also have the flexibility to synchronize initialization of multiple devices or to
delay initialization with the CLKUSR option. The CLKUSR pin allows you to control
when your device enters user mode for an indefinite amount of time. You can turn on
the Enable user-supplied start-up clock (CLKUSR) option in the Quartus II software
from the General tab of the Device and Pin Options dialog box. When you turn on
9–61.
chapters.
Cyclone III Device Data Sheet
Cyclone III Device Handbook, Volume 1
“JTAG Instructions”
and
9–9