EP3C55F484C8N Altera, EP3C55F484C8N Datasheet - Page 176

• Manufacturer Part Number: EP3C55F484C8N
• Description: IC CYCLONE III FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C55F484C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2396160
• Number Of I /o: 327
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 327
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 3491
• Family Type: Cyclone III
• No. Of I/o's: 327
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2510

9–16
Cyclone III Device Handbook, Volume 1
1
1
1
The first Cyclone III device family in the chain is the configuration master and
controls the configuration of the entire chain. You must connect its MSEL pins to
select the AS configuration scheme. The remaining Cyclone III device family is
configuration slaves and you must connect their MSEL pins to select the PS
configuration scheme. Any other Altera device that supports PS configuration can
also be part of the chain as a configuration slave.
When connecting a serial configuration device to the Cyclone III device family in the
multi-device AS configuration, you must connect a 25-Ω series resistor at the near end
of the serial configuration device for DATA[0].
In the multi-device AS configuration, the board trace length between the serial
configuration device to the master device of the Cyclone III device family must follow
the recommendations in
buffers between the master and slave devices of the Cyclone III device family for
DATA[0] and DCLK. All I/O inputs must maintain a maximum AC voltage of 4.1 V.
The output resistance of the repeater buffers must fit the maximum overshoot
equation outlined in
As shown in
devices are connected together with external pull-up resistors. These pins are
open-drain bidirectional pins on the devices. When the first device asserts nCEO (after
receiving all its configuration data), it releases its CONF_DONE pin. However, the
subsequent devices in the chain keep this shared CONF_DONE line low until they
receive their configuration data. When all target devices in the chain receive their
configuration data and release CONF_DONE, the pull-up resistor drives a high level on
this line and all devices simultaneously enter initialization mode.
Although you can cascade Cyclone III device family, serial configuration devices
cannot be cascaded or chained together.
If the configuration bitstream size exceeds the capacity of a serial configuration
device, you must select a larger configuration device, enable the compression feature,
or both. When configuring multiple devices, the size of the bitstream is the sum of the
individual devices configuration bitstreams.
Configuring Multiple Cyclone III Device Family with the Same Design
Certain designs require you to configure multiple Cyclone III device family with the
same design through a configuration bitstream or a .sof. You can do this using the
following methods:
■
■
Multiple SRAM Object Files
Single SRAM Object File
1
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
For both methods, the serial configuration devices cannot be cascaded or
chained together.
Figure 9–4 on page
“Configuration and JTAG Pin I/O Requirements” on page
Table 9–9 on page
9–15, the nSTATUS and CONF_DONE pins on all target
9–20. You must also connect the repeater
© December 2009 Altera Corporation
Configuration Features
9–7.