EP3C55F484C8N Altera, EP3C55F484C8N Datasheet - Page 175

• Manufacturer Part Number: EP3C55F484C8N
• Description: IC CYCLONE III FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C55F484C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2396160
• Number Of I /o: 327
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 327
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 3491
• Family Type: Cyclone III
• No. Of I/o's: 327
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2510

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
Figure 9–4. Multi-device AS Configuration
Notes to
(1) Connect the pull-up resistors to the V
(2) Connect the pull-up resistor to the V
(3) You can leave the nCEO pin unconnected or use it as a user I/O pin when it does not feed the nCE pin of another device.
(4) The MSEL pin settings vary for different configuration voltage standards and POR time. You must set the master device of the Cyclone III device
(5) These are dual-purpose I/O pins. The nCSO pin functions as the FLASH_NCE pin in AP mode. The ASDO pin functions as the DATA[1] pin in
(6) Connect the series resistor at the near end of the serial configuration device.
(7) Connect the repeater buffers between the master and slave devices of the Cyclone III device family for DATA[0] and DCLK. All I/O inputs must
(8) The 50-Ω series resistors are optional if the 3.3-V configuration voltage standard is applied. For optimal signal integrity, connect these 50-Ω series
© December 2009
family in AS mode and the slave devices in PS mode. To connect MSEL[3..0] for the master device in AS mode and slave devices in PS mode,
refer to
other AP and FPP modes.
maintain a maximum AC voltage of 4.1 V. The output resistance of the repeater buffers must fit the maximum overshoot equation outlined in
“Configuration and JTAG Pin I/O Requirements” on page
resistors if the 2.5- or 3.0-V configuration voltage standard is applied.
Figure
Serial Configuration
Table 9–7 on page
9–4:
Device
Altera Corporation
DCLK
DATA
ASDI
nCS
10
kΩ
V CCIO (1)
25
50
9–11. Connect the MSEL pins directly to V
Ω
Ω
(6)
(6), (8)
10
kΩ
V CCIO (1)
CCIO
CCIO
supply voltage of the I/O bank in which the nCE pin resides.
10
supply of the bank in which the pin resides.
kΩ
GND
V CCIO (1)
DATA[0]
DCLK
nCSO (5)
ASDO (5)
nSTATUS
CONF_DONE
nCONFIG
nCE
Cyclone III Device Family
Master Device of the
Buffers (7)
50
9–7.
Ω
(8)
MSEL[3..0]
nCEO
CCA
or GND.
10
(4)
kΩ
V CCIO (2)
Slave Device of the Cyclone III Device Family
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA[0]
DCLK
Cyclone III Device Handbook, Volume 1
MSEL[3..0]
nCEO
N.C. (3)
(4)
9–15