EP3C120F780I7 Altera, EP3C120F780I7 Datasheet - Page 46

• Manufacturer Part Number: EP3C120F780I7
• Description: IC CYCLONE III FPGA 120K 780FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C120F780I7

• Number Of Logic Elements/cells: 119088
• Number Of Labs/clbs: 7443
• Total Ram Bits: 3981312
• Number Of I /o: 531
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 119088
• # I/os (max): 531
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 119088
• Ram Bits: 3981312
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FBGA
• For Use With: 544-2589 - KIT DEV EMB CYCLONE III EDITION544-2566 - KIT DEV DSP CYCLONE III EDITION544-2444 - KIT DEV CYCLONE III EP3C120
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

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A comprehensive static timing analysis includes analysis of register-to-register, I/O,
and asynchronous reset paths. It is important to specify the frequencies and
relationships for all clocks in your design. Use input and output delay constraints to
specify external device or board timing parameters. The Timing Analyzer performs
static timing analysis on the entire system, using data required times, data arrival
times, and clock arrival times to verify circuit performance and detect possible timing
violations. You can use the report_datasheet command to generate a datasheet
report that summarizes the I/O timing characteristics of the entire design. For
asynchronous control signals; for example clear, reset and load signal of a register,
perform the recovery and removal timing analysis. Use the -recovery and
-removal options together with the report_timing command for the TimeQuest
Timing Analyzer.
Multicycle paths are data paths that require more than one clock cycle to latch data at
the destination register. For example, a register only captures data on every second or
third rising clock edge. For multicycle paths, the default setup and hold relationships
can be modified with the set_multicycle_path command to accommodate the
system requirement.
For more information about timing analysis, refer to the
Analyzer
Handbook.
For more information about the TimeQuest Timing Analyzer and the Classic Timing
Analyzer, refer to the
Timing Analyzer
Early Timing Estimation
You can estimate your design’s timing with the Quartus II Early Timing Estimation.
The Early Timing Estimation provides preliminary timing information without
performing a full compilation of your design. To save compilation time, the fitter does
not perform a full optimization, thus the timing information is only an estimate. On
the Processing menu, point to Start and click Start Early Timing Estimate to generate
initial compilation results after you have run analysis and synthesis.
You can set the Early Timing Estimation Level to Realistic, Optimistic, or
Pessimistic, as in
obtained with a full fit when the realistic setting is used. Early Timing Estimate
generates a full timing report based on the early placement and routing delays.
or
Synopsys PrimeTime Support
chapters, respectively, in volume 3 of the Quartus II Handbook.
Figure
Quartus II TimeQuest Timing Analyzer
8. Typically, the estimated delays are within 10% of those
chapter in volume 3 of the Quartus II
Quartus II TimeQuest Timing
© November 2008 Altera Corporation
and the
Quartus II Classic
Verification