EP3C120F780I7 Altera, EP3C120F780I7 Datasheet - Page 48

IC CYCLONE III FPGA 120K 780FBGA

EP3C120F780I7

Manufacturer Part Number
EP3C120F780I7
Description
IC CYCLONE III FPGA 120K 780FBGA
Manufacturer
Altera
Series
Cyclone® IIIr

Specifications of EP3C120F780I7

Number Of Logic Elements/cells
119088
Number Of Labs/clbs
7443
Total Ram Bits
3981312
Number Of I /o
531
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
119088
# I/os (max)
531
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
119088
Ram Bits
3981312
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FBGA
For Use With
544-2589 - KIT DEV EMB CYCLONE III EDITION544-2566 - KIT DEV DSP CYCLONE III EDITION544-2444 - KIT DEV CYCLONE III EP3C120
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant

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Page 48
Verification
I/O Timing Analysis
Perform I/O analysis with the TimeQuest Timing Analyzer or Classic Timing
Analyzer to ensure that the Cyclone III device meets the timing requirement when
interfacing with external devices on the board. If you know the maximum or
minimum delay of a signal from a register of an external device to a specified input or
bidirectional pin on the Cyclone III device relative to a specified clock source, use the
Input Delay assignment.
For the registered output from the Cyclone III device, you can make the Output Delay
assignment for maximum or minimum delay of a signal from the registered output of
the Cyclone III device to the registered input of the external device, relative to a
specified clock source.
Skew Management
Skew refers to the arrival time difference of a signal at two different destinations. For
synchronous designs, we have clock and data skew due to the different path length of
the clock and data signals. The effect of the skew is more significant on high speed
signals, due to the short time period of the signals. Using the clock network for these
high speed signals results in lower clock and data skew.
Use the Quartus II Maximum Clock Arrival Skew assignment to specify the
maximum allowable clock arrival skew between a clock signal and various
destination registers. For data signals, use the Maximum Data Arrival Skew
assignment to specify the maximum allowable data arrival skew to various
destination registers or pins. When these assignments are used, the Quartus II
software determines the timing difference between the longest clock or data path, and
the shortest clock or data path so that the Fitter attempts to meet the requirement.
Area and Timing Optimization
Physical synthesis optimizations make placement-specific changes to the netlist that
improve results for a specific Altera device. You can specify Physical synthesis for
performance or Physical synthesis for fitting options under the Fitter Settings, as in
Figure
9. These options typically increase compilation time significantly but can
provide significant improvements to the compilation result. If you turn on these
options, ensure that they do improve the results for your design.
© November 2008 Altera Corporation

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