EP3C120F780I7 Altera, EP3C120F780I7 Datasheet - Page 50

IC CYCLONE III FPGA 120K 780FBGA

EP3C120F780I7

Manufacturer Part Number
EP3C120F780I7
Description
IC CYCLONE III FPGA 120K 780FBGA
Manufacturer
Altera
Series
Cyclone® IIIr

Specifications of EP3C120F780I7

Number Of Logic Elements/cells
119088
Number Of Labs/clbs
7443
Total Ram Bits
3981312
Number Of I /o
531
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
119088
# I/os (max)
531
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
119088
Ram Bits
3981312
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FBGA
For Use With
544-2589 - KIT DEV EMB CYCLONE III EDITION544-2566 - KIT DEV DSP CYCLONE III EDITION544-2444 - KIT DEV CYCLONE III EP3C120
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant

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Page 50
Figure 10. Design Space Explorer Window
f
f
For more information, refer to the
Quartus II Handbook.
The Optimization Advisors provide guidance in making settings that optimize your
design. On the Tools menu, point to Advisors, and click Resource Optimization
Advisor, or Timing Optimization Advisor. Evaluate the options and choose the
settings that best suit the requirements.
For more information about the various timing optimization settings in the Quartus II
software as well as the timing optimization techniques, refer to the
Integrated Synthesis
Timing Optimization
Recommended Timing Optimization and Analysis Assignments
The assignments and settings described in this section are not turned on in the
software by default for all designs, but are important for large designs.
Turn on Optimize fast-corner timing on the Fitter Settings page in the Settings
dialog box, as in
timing requirements at the Fast Timing process corner and operating condition, as
well as at the Slow Timing corner. Therefore, turning on this option helps create a
design implementation that is more robust across process, temperature, and voltage
variations.
Figure
chapter in volume 1 of the Quartus II Handbook and the
chapter in volume 2 of the Quartus II Handbook.
11. When this option is on, the design is optimized to meet its
Design Space Explorer
chapter in volume 2 of the
© November 2008 Altera Corporation
Quartus II
Area and
Verification

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