EP3C120F780I7 Altera, EP3C120F780I7 Datasheet - Page 58

• Manufacturer Part Number: EP3C120F780I7
• Description: IC CYCLONE III FPGA 120K 780FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C120F780I7

• Number Of Logic Elements/cells: 119088
• Number Of Labs/clbs: 7443
• Total Ram Bits: 3981312
• Number Of I /o: 531
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 119088
• # I/os (max): 531
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 119088
• Ram Bits: 3981312
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FBGA
• For Use With: 544-2589 - KIT DEV EMB CYCLONE III EDITION544-2566 - KIT DEV DSP CYCLONE III EDITION544-2444 - KIT DEV CYCLONE III EP3C120
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

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Quick Design Debugging Using SignalProbe chapter in volume 3 of the Quartus II
Handbook
Design Debugging Using the SignalTap II Embedded Logic Analyzer chapter in volume
3 of the Quartus II Handbook
In-System Debugging Using External Logic Analyzers chapter in volume 3 of the
Quartus II Handbook
In-System Updating of Memory and Constants chapter in volume 3 of the Quartus II
Handbook
Design Debugging Using In-System Sources and Probes chapter in volume 3 of the
Quartus II Handbook
sld_virtual_jtag Megafunction User Guide
AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O
Systems
I/O Management chapter in volume 2 of the Quartus II Handbook
AN 508: Cyclone III Simultaneous Switching Noise (SSN) Design Guidelines
AN 224: High-Speed Board Layout Guidelines
AN 315: Guidelines for Designing High-Speed FPGA PCBs
Signal Integrity Analysis with Third-Party Tools chapter in volume 3 of the Quartus II
Handbook
Cyclone III Device Family Pin Connection Guidelines
Hot Socketing and Power-On Reset in Cyclone III Devices chapter in volume 1 of the
Cyclone III Device Handbook
JTAG Configuration and ISP Troubleshooter
FPGA Configuration Troubleshooter
Recommended HDL Coding Styles chapter in volume 1 of the Quartus II Handbook
Synthesis in volume 1 of the Quartus II Handbook
Volume 4: SOPC Builder of the Quartus II Handbook
Design Recommendations for Altera Devices and the Quartus II Design Assistant
chapter in volume 1 of the Quartus II Handbook
altclkctrl Megafunction User Guide
altpll Megafunction User Guide
Incremental Compilation for Hierarchical and Team-Based Design chapter in volume 1
of the Quartus II Handbook
Analyzing and Optimizing the Design Floorplan chapter in volume 2 of the Quartus II
Handbook
Power Optimization chapter in volume 2 of the Quartus II Handbook
Design Space Explorer chapter in volume 2 of the Quartus II Handbook
Quartus II Classic Timing Analyzer chapter of the Quartus II Handbook
Software Settings section in volume 2 of the Configuration Handbook
© November 2008 Altera Corporation
Referenced Documents