AT94K10AL-25AJI Atmel, AT94K10AL-25AJI Datasheet - Page 109

• Manufacturer Part Number: AT94K10AL-25AJI
• Description: IC FPSLIC 10K GATE 25MHZ 84PLCC
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K10AL-25AJI

• Core Type: 8-bit AVR
• Speed: 25MHz
• Interface: I²C, UART
• Program Sram Bytes: 20K-32K
• Fpga Sram: 4kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 576
• Fpga Gates: 10K
• Fpga Registers: 846
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

1138I–FPSLI–1/08
Figure 4-33. Effects on Unsynchronized OCR1 Latching
Note:
Figure 4-34. Effects of Unsynchronized OCR1 Latching in Overflow Mode
Note:
During the time between the write and the latch operation, a read from OCR1A or OCR1B will
read the contents of the temporary location. This means that the most recently written value
always will read out of OCR1A/B.
When the OCR1X contains $0000 or TOP, and the up/down PWM mode is selected, the output
OC1A/OC1B is updated to Low or High on the next compare match according to the settings of
COM1A1/COM1A0 or COM1B1/COM1B0. This is shown in
the output OC1A/OC1B is held Low or High only when the Output Compare Register contains
TOP.
Compare Value Changes
1. X = A or B
1. X = A or B
Unsynchronized
Synchronized
Unsynchronized OC1x
Compare Value Changes
Synchronized OC1x
OCR1X
OCR1X
(1)
(1)
(1)
Latch
Latch
(1)
Latch
Latch
AT94KAL Series FPSLIC
Compare Value Changes
Compare Value Changes
Glitch
Table
4-22. In overflow PWM mode,
PWM Output OC1x
PWM Output OC1x
Compare Value
Counter Value
PWM OutputOC1X
Counter Value
Compare Value
PWM OutputOC1X
(1)
(1)
(1)
(1)
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