AT94K10AL-25AJI Atmel, AT94K10AL-25AJI Datasheet - Page 156

• Manufacturer Part Number: AT94K10AL-25AJI
• Description: IC FPSLIC 10K GATE 25MHZ 84PLCC
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K10AL-25AJI

• Core Type: 8-bit AVR
• Speed: 25MHz
• Interface: I²C, UART
• Program Sram Bytes: 20K-32K
• Fpga Sram: 4kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 576
• Fpga Gates: 10K
• Fpga Registers: 846
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Table 4-32.
156
(TWSR)
Status
Code
$C0
$C8
$A8
$B0
$B8
AT94KAL Series FPSLIC
Own SLA+R has been
received;
ACK has been returned
Arbitration lost in
SLA+R/W as Master;
own SLA+R has been
received;
ACK has been returned
Data byte in TWDR has
been transmitted;
ACK has been received
Data byte in TWDR has
been transmitted;
NOT ACK has been
received
Last data byte in TWDR
has been transmitted
(TWAE = “0”);
ACK has been received
Serial Bus and 2-wire
Status of the 2-wire
Serial Hardware
Status Codes for Slave Transmitter Mode
Load data byte or
Load data byte
Load data byte or
Load data byte
Load data byte or
Load data byte
No TWDR action or
No TWDR action or
No TWDR action or
No TWDR action
No TWDR action or
No TWDR action or
No TWDR action or
No TWDR action
To/From TWDR
Application Software Response
STA
X
X
X
X
X
X
0
0
1
1
0
0
1
1
STO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
To TWCR
TWINT
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TWEA
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Last data byte will be transmitted and NOT
ACK should be received
Data byte will be transmitted and ACK should
be received
Last data byte will be transmitted and NOT
ACK should be received
Data byte will be transmitted and ACK should
be received
Last data byte will be transmitted and NOT
ACK should be received
Data byte will be transmitted and ACK should
be received
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA
Switched to the not addressed Slave mode;
own SLA will be recognized; GCA will be
recognized if GC = “1”
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA; a START
condition will be transmitted when the bus
becomes free
Switched to the not addressed Slave mode;
own SLA will be recognized; GCA will be
recognized if GC = “1”; a START condition
will be transmitted when the bus becomes
free
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA
Switched to the not addressed Slave mode;
own SLA will be recognized; GCA will be
recognized if GC = “1”
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA; a START
condition will be transmitted when the bus
becomes free
Switched to the not addressed Slave mode;
own SLA will be recognized; GCA will be
recognized if GC = “1”; a START condition
will be transmitted when the bus becomes
free
Next Action Taken by 2-wire
Serial Hardware
1138I–FPSLI–1/08