AT94K10AL-25AJI Atmel, AT94K10AL-25AJI Datasheet - Page 8

• Manufacturer Part Number: AT94K10AL-25AJI
• Description: IC FPSLIC 10K GATE 25MHZ 84PLCC
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K10AL-25AJI

• Core Type: 8-bit AVR
• Speed: 25MHz
• Interface: I²C, UART
• Program Sram Bytes: 20K-32K
• Fpga Sram: 4kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 576
• Fpga Gates: 10K
• Fpga Registers: 846
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

2.7
2.8
8
Cell Connections
The Cell
AT94KAL Series FPSLIC
In
neighbors. Section (b) of
buses (one per busing plane) and five vertical local buses (one per busing plane).
Figure 2-3.
Figure 2-4
muxes and pass gates are independent. All permutations of programmable muxes and pass
gates are legal. Vn is connected to the vertical local bus in plane n. Hn is connected to the hori-
zontal local bus in plane n. A local/local turn in plane n is achieved by turning on the two pass
gates connected to Vn and Hn. Up to five simultaneous local/local turns are possible.
The logic cell can be configured in several “modes”. The logic cell flexibility makes the FPGA
architecture well suited to all digital design application areas, see
automatically optimizes designs to utilize the cell flexibility.
Figure 2-3
CELL
CELL
CELL
depicts the AT40K FPGA embedded core logic cell. Configuration bits for separate
section (a) depicts direct connections between an FPGA cell and its eight nearest
Cell Connections
(a) Cell-to-Cell Connections
Figure 2-3
Y
X
X
CELL
CELL
CELL
Y
Y
X
X
Y
shows the connections between a cell five horizontal local
CELL
CELL
CELL
Figure
(b) Cell-to-Bus Connections
2-5. The IDS layout tool
W
X
Y
Z
L
WXYZL
CELL
1138I–FPSLI–1/08