AT94K10AL-25AJI Atmel, AT94K10AL-25AJI Datasheet - Page 180

• Manufacturer Part Number: AT94K10AL-25AJI
• Description: IC FPSLIC 10K GATE 25MHZ 84PLCC
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K10AL-25AJI

• Core Type: 8-bit AVR
• Speed: 25MHz
• Interface: I²C, UART
• Program Sram Bytes: 20K-32K
• Fpga Sram: 4kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 576
• Fpga Gates: 10K
• Fpga Registers: 846
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

6.6
CMOS buffer delays are measured from a V
stant. Buffer delay is to a pad voltage of 1.5V with one output switching. Parameter based on characterization and
simulation; not tested in production. An FPGA power calculation is available in Atmel’s System Designer software (see also
page
180
Cell Function
Async RAM
Write
Write
Write
Write
Write
Write
Write
Write
Write/Read
Read
Read
Read
Sync RAM
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write/Read
Write/Read
Read
Read
Read
171).
AC Timing Characteristics – 3.3V Operation
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: V
Minimum times based on best case: V
AT94KAL Series FPSLIC
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WECYC
WEL
WEH
setup
hold
setup
hold
hold
PD
PD
PZX
PXZ
CYC
CLKL
CLKH
setup
hold
setup
hold
setup
hold
PD
PD
PD
PZX
PXZ
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Minimum)
(Minimum)
(Minimum)
(Maximum)
(Maximum)
(Minimum)
(Minimum)
(Minimum)
(Maximum)
(Maximum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
CC
CC
= 3.6V, temperature = 0° C
IH
= 3.0V, temperature = 70° C
Path
cycle time
we
we
wr addr setup-> we
wr addr hold -> we
din setup -> we
din hold -> we
oe hold -> we
din -> dout
rd addr -> dout
oe -> dout
oe -> dout
cycle time
clk
clk
we setup-> clk
we hold -> clk
wr addr setup-> clk
wr addr hold -> clk
wr data setup-> clk
wr data hold -> clk
din -> dout
clk -> dout
rd addr -> dout
oe -> dout
oe -> dout
of 1/2 V
CC
at the pad to the internal V
12.0
12.0
-25
5.0
5.0
5.3
0.0
5.0
0.0
0.0
8.7
6.3
2.9
3.5
5.0
5.0
3.2
0.0
5.0
0.0
3.9
0.0
8.7
5.8
6.3
2.9
3.5
IH
Units
at A. The input buffer load is con-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
–
Pulse Width Low
Pulse Width High
–
–
rd addr = wr addr
–
–
Pulse Width High
–
–
–
rd addr = wr addr
rd addr = wr addr
–
1138I–FPSLI–1/08