MPC8379EVRAJF Freescale Semiconductor, MPC8379EVRAJF Datasheet

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... Mbps Ethernet interfaces, a DDR1/DDR2 SDRAM memory controller, a flexible, a 32-bit local bus controller, a 32-bit PCI controller, an optional dedicated security engine, a USB © Freescale Semiconductor, Inc., 2008–2010. All rights reserved. Document Number: MPC8379EEC Rev. 4, 11/2010 Contents 1 ...

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... D-Cache I-Cache USB 2.0 eTSEC Hi-Speed RGMII, RMII, RGMII, RMII, Host Device RTBI, MII RTBI, MII 2 C controllers, a 4-channel DMA Figure 1 DDR1/DDR2 Enhanced SDRAM Local Bus Controller SD/MMC SATA eTSEC Controller PHY PHY PHY PHY Freescale Semiconductor shows the ...

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... Enhanced host controller interface (EHCI) compatible • Supports high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operation; low-speed operation is supported only in host mode • Supports UTMI + low pin interface (ULPI) MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor MPC8377E MPC8378E ...

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... The device provides an integrated four-channel DMA controller with the following features: • Allows chaining (both extended and direct) through local memory-mapped chain descriptors (accessible by local masters) • Supports misaligned transfers MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev DUART, Enhanced Local Bus Controller Freescale Semiconductor ...

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... Single 32-bit data PCI interface operates MHz • PCI 3.3-V compatible (not 5-V compatible) • Support for host and agent modes • On-chip arbitration, supporting 5 external masters on PCI • Selectable hardware-enforced coherency MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Overview 5 ...

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... This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8379E. The device is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev Freescale Semiconductor ...

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... IN REF the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation shown in Figure 2. 6 L[1,2]_nV includes SDAV _0, XCOREV DD DD MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Table 2. Absolute Maximum Ratings Symbol and OV DD LBV L[1,2]_nV ...

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... V ± 165 2.5 V ± 125 mV OV 3.3 V ± 165 LBV 1.8 V ± 2.5 V ± 125 mV 3.3 V ± 165 mV 1.0 ± 1.05 V ± ° (min)— =125 (max ° =–40 (min)— =125 (max Freescale Semiconductor are Notes — 1 — — — ...

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... GPIO signals 1 Specialized SerDes output capabilities are described in the relevant section of the specification (such as SATA) MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Not to Exceed 10% of tinterface1 refers to the clock period associated with the bus clock interface. Table 4. Output Drive Capability 1 Output Impedance (Ω ...

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... AV ) before the I/O voltages and DD and AV must reach 90% of their DD Figure 3. I/O voltage AVDD Table 5. 1 Typical Application Max Application 125°C ( 125°C ( 3.2 3.0 3.3 3.1 Freescale Semiconductor 4 3.8 3.6 4.0 3.8 ...

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... Typical power is based on a voltage of V 800 MHz, and running a Dhrystone benchmark application. 4 Maximum power is based on a voltage 800 MHz, worst case process, and running an artificial smoke test. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 1 (continued) Sleep Power Typical Application 65° ...

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... L[1,2]_nV DD Unit Comments (1.0 V) — W — — W — W — W — W — W — W — W — W — W — W — — W — W — — W — W — W — W Freescale Semiconductor ...

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... Table 7. CLKIN DC Electrical Characteristics Parameter Input high voltage Input low voltage CLKIN Input current PCI_CLK Input current OV Note PCI agent mode, this specification does not comply with PCI 2.3 Specification. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor GV /LBV (2.5 V) (3.3 V) (3.3 V) — ...

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... Typical Max Unit 125 — MHz 8 — ns — ns 0.75 1.0 — — ±150 ps = 2.5 V and from 0.6 and 2.7 V for DD for the duty cycle for 10Base-T and 100Base-T Freescale Semiconductor Notes 1, 6 — Notes — — ...

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... Input setup time for POR config signals (CFG_RESET_SOURCE[0:3], CFG_CLKIN_DIV, and CFG_LBMUX) with respect to negation of PORESET when the device is in PCI agent mode Input hold time for POR config signals with respect to negation of HRESET MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Symbol Condition V — ...

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... GV MV REF – 0.04 TT REF 0.140 IH REF V –0 – –13.4 OH Min Max Unit Notes — — PCI_SYNC_IN Unit Notes μs — (typ (typ Max Unit Notes 1. 0.51 × 0. REF GV + 0.3 V — – 0.140 V — REF μ — mA — Freescale Semiconductor ...

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... MV . This rail should track variations in the DC level of MV REF 4 Output leakage is measured with all outputs disabled See AN3665, “MPC837xE Design Checklist,” for proper DDR termination. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Symbol Min I 13 all times and to track GV DC variations as measured at the receiver ...

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... V DD Max Unit — 0 /2, V (peak-to-peak) = 0.2 V. OUT DD OUT REF Typ Max Unit μA 250 600 150 400 VDD(typ) G Max MV – 0.25 REF + 0.25 — (typ Max MV – 0.31 REF + 0.31 — Freescale Semiconductor Notes 1 1 Note Unit V V Unit V V ...

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... MHz data rate MCSn output hold with respect to MCK 400 MHz data rate 333 MHz data rate 266 MHz data rate 200 MHz data rate MCK to MDQS skew MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Symbol Min t CISKEW –500 –750 –750 = ± ...

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... DDR timing (DD) for the time t DDKLDX Max Unit Notes — — — — — — — — –0.5 × 0 MCK 0 for memory clock reference MCK describes the DDR timing (DD) DDKHMH can be modified through control DDKHMH follows the symbol DDKHMP Freescale Semiconductor ...

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... Figure 5 shows the DDR1 and DDR2 SDRAM output timing diagram. MCK[n] MCK[n] ADDR/CMD Write A0 MDQS[n] MDQ[x] Figure 5. DDR1 and DDR2 SDRAM Output Timing Diagram MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor MCK[n] MCK[n] t MCK t DDKHMHmax) = 0.6 ns MDQS t DDKHMH(min) = –0.6 ns MDQS Figure 4 ...

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... IN symbol referenced in Table IN Table 23. DUART AC Timing Specifications th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are GVDD Ω Max OV + 0.3 DD 0.8 — 0.2 ±30 2. Value Unit 256 baud > 1,000,000 baud 16 — Freescale Semiconductor Unit μA Notes — ...

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... IN DD2 Input low current (V = GND) IN Note supports eTSEC 1. DD1 LV supports eTSEC 2. DD2 MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC) Table 25 are based on a 2.5 V CMOS interface voltage as Symbol Min LV 3.13 DD1 LV DD2 V 2.40 LV /LV ...

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... Symbol t MTX t MTX t t MTXH/ MTX t MTKHDX Max Unit Notes 2. /LV + 0.3 V DD1 DD2 0. /LV + 0.3 V DD1 DD2 0.70 V μA –20 μA — Min Typical Max — 400 — — 40 — 35 — Freescale Semiconductor 1, 2 — — — — — Unit ...

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... Input low voltage Input high voltage RX_CLK clock period 10 Mbps RX_CLK clock period 100 Mbps RX_CLK duty cycle RXD[3:0], RX_DV, RX_ER setup time to RX_CLK RXD[3:0], RX_DV, RX_ER hold time to RX_CLK MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor of 3.3 V ± 5 Symbol t MTXR t ...

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... Symbol Min t –600 SKRGT t 1.0 SKRGT t 7.2 RGT Min Typical Max 1.0 — 4.0 1.0 — 4.0 symbolizes MII MRDVKH clock reference MRX LVDD Ω MRXR t MRDXKL Typical Max Unit 0 600 ps — 2.8 ns 8.0 8.8 ns Freescale Semiconductor Unit ns ns Notes — ...

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... This symbol represents the external EC_GTX_CLK125 and does not follow the original signal naming convention. Figure 10 provides the AC test load for eTSEC. Output MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC) of 2.5 V ± 5 Symbol Min ...

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... TXD[8:5] TXD[3:0] TXD[7:4] TXD[9] TXD[4] TXEN TXERR RXD[8:5] RXD[3:0] RXD[7:4] t SKRGT RXD[4] RXD[9] RXDV RXERR Table 29. of 3.3 V ± 5 Symbol t RMT t RMTH t RMTJ t RMTR t RGT t SKRGT t SKRGT Min Typical Max 15.0 20.0 25 — — 250 1.0 — 2.0 Freescale Semiconductor Unit ...

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... DD Input high voltage at 3 REF_CLK clock period REF_CLK duty cycle REF_CLK peak-to-peak jitter Rise time REF_CLK (20%–80%) Fall time REF_CLK (80%–20%) MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor of 3.3 V ± 5 Symbol t RMTF t RMTDX (first two letters of functional block)(signal)(state) (reference)(state) for outputs ...

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... RMRF RMRH Valid Data t RMRDV Figure 14. RMII Receive AC Timing Diagram = 50 Ω Figure 15. eTSEC AC Test Load 1 Min Typical Max 4.0 — — 2.0 — — symbolizes MII MRDVKH clock reference MRX LVDD Ω RMRR t RMRDX LVDD Ω Freescale Semiconductor Unit ns ns ...

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... Table 33. MII Management AC Timing Specifications Parameter MDC frequency MDC period MDC clock pulse width high MDC to MDIO valid MDC to MDIO delay MDIO to MDC setup time MDIO to MDC hold time MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Table 31 and Conditions Symbol — LV DD1 LV = Min ...

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... MDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the t MDC t t MDCH MDCF MDDVKH t t MDDXKH t MDKHDX Max Unit — — symbolizes MDKHDX t MDCR Freescale Semiconductor Notes 4 4 ...

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... For active/float timing measurements, the high impedance or off state is defined to be when the total current delivered through the component pin is less than or equal to that of the leakage current specification. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Table 34. USB DC Electrical Characteristics Symbol ...

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... DC electrical characteristics for the local bus interface Conditions Symbol — LBV LBV = Min 4.0 mA LBV = Min V DD — — V — — LBV GND Ω USIXKH = 3 Min Max 3.135 3.465 DD 2.40 — OH — 0.50 OL 2.0 LBV + 0 –0.3 0. — –30 — IL Freescale Semiconductor Unit μA μA ...

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... LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) Local bus clock to LALE rise Local bus clock to output valid (except LALE) MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor = 2 Conditions — ...

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... LBK /2 and the 0.4 × LBV the rising/falling edge of LSYNC_IN to 0.5 × LBV DD Min Max Unit — 3 — ns symbolizes local bus LBIXKH1 clock reference (K) goes high (H), in this case for of the signal in question the signal in question. DD Freescale Semiconductor Notes ...

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... For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. Figure 19 provides the AC test load for the local bus. Output MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 1 Symbol t LBK t ...

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... LAD[0:31]/LDP[0:3] Output (Address) Signal: LAD[0:31] LALE Figure 20. Local Bus Signals, Non-special Signals Only (PLL Enable Mode) MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev LBIVKH t LBIVKH t LBKHOX t LBKHOV t LBKHOZ t LBKHOX t LBKHOV t LBKHOZ t LBKHOX t LBKHOV t t LBOTOT LBKHLR t LBIXKH t LBIXKH Freescale Semiconductor ...

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... LGTA Output Signals: LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] LA[27:31]/LBCTL/LBCKE/LOE Output (Data) Signals: LAD[0:31]/LDP[0:3] Output (Address) Signal: LAD[0:31] LALE Figure 21. Local Bus Signals, Non-special Signals Only (PLL Bypass Mode) MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor t LBIVKH t LBKHOV t LBKHOZ t LBKHOV t LBKHOZ t ...

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... Output (Data) Signals: LAD[0:31]/LDP[0:3] Output (Address) Signal: LAD[0:31] Figure 22. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV (PLL Enable Mode) MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev LBKHOV LBKHOX t LBIVKH t LBIVKH t LBKHOX t LBKHOV t LBKHOZ t LBKHOX t LBKHOV t LBKHOZ t LBKHOX t LBKHOV t LBIXKH t LBIXKH Freescale Semiconductor ...

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... LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:1]/LGPL[0:5] Output (Data) Signals: LAD[0:31]/LDP[0:3] Output (Address) Signal: LAD[0:31] Figure 23. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV (PLL Bypass Mode) MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor t LBKHOZ t LBKHOV t LBIVKH t t ...

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... Output (Data) Signals: LAD[0:31]/LDP[0:3] Output (Address) Signal: LAD[0:31] Figure 24. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV (PLL Enable Mode) MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev LBKHOZ t LBKHOV t LBIVKH t LBIVKH t LBKHOX t LBKHOV t LBKHOZ t LBKHOX t LBKHOV t LBKHOZ t LBKHOX t LBKHOV t LBIXKH t LBIXKH Freescale Semiconductor ...

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... SD_DAT[0:3]/CMD as outputs and sample the SD_DAT[0:3] as inputs. This behavior is true for both full- and high-speed modes. Note that this is a non-standard implementation, as the SD card specification assumes that in high-speed mode, data is driven at the rising edge of the clock. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Enhanced Secure Digital Host Controller (eSDHC) t LBKHOZ t ...

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... SFSCKR t SFSCKF t SFSIVKH Min Max 0.625 × 0 0.25 × OV –0.3 DD — ±30 0.75 × OV — DD 0.125 × OV — DD Figure 27 Min Max Unit 0 25 MHz 40 — 400 KHz 15 — — ns — — ns Freescale Semiconductor Unit V V μ and Notes — — — ...

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... For reference only, according to the SD card specifications. 4 Average, for reference only. Figure 26 provides the eSDHC clock input timing diagram. eSDHC External Clock operational mode Figure 26. eSDHC Clock Input Timing Diagram MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor = 3.3 V ± 165 mV Symbol t SFSIXKH t INT_CLK_DLY t ...

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... SFSKHOV DATA_DELAY ISU SFSCKL + < t DATA_DELAY ISU SFSCKL + t < SFSCKL SFSCK CLK_DELAY 5 4 – – CLK_DELAY < SFSCKL SFSKHOX DATA_DELAY CLK_DELAY Sampling Edge t SFSCKL ns) ISU + t CLK_DELAY t t – – ISU SFSKHOV = 20 ns: SFSCKL t – IH Freescale Semiconductor Eqn. 1 Eqn. 2 Eqn. 3 Eqn. 4 ...

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... Full-Speed Read Meeting Setup (Maximum Delay) The following equations show how to calculate the allowed combined propagation delay range of the SD_CLK and SD_DAT/CMD signals on the PCB. t CLK_DELAY CLK_DELAY MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor + t t < – IH SFSKHOX SFSCKL DATA_DELAY < ...

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... SHSCKL t SHSCKH t SHSCKR/ t SHSCKF t SHSIVKH t SHSIXKH t SHSKHOV t SHSKHOX t INT_CLK_DLY t ISU ODLY SFSIXKH Figure 30 Min Max Unit 0 50 MHz 20 — 400 KHz 7 — — ns — — — ns — — ns 1.5 — — — ns — Freescale Semiconductor Eqn. 9 and Notes — — — ...

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... Average, for reference only. Figure 29 provides the eSDHC clock input timing diagram. eSDHC External Clock operational mode Figure 29. eSDHC Clock Input Timing Diagram MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor = 3.3 V ± 165 mV Symbol t OH (first three letters of functional block)(signal)(state) ...

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... Edge t CLK_DELAY SHSKHOV t SHSCKL SHSKHOX t DATA_DELAY t (6 ns) ISU Figure 30. High Speed Output Path + < t DATA_DELAY ISU SHSCKL + < DATA_DELAY ISU SHSCKL t < – – CLK_DELAY SHSCKL ISU < – – < 0 Sampling Edge t (2 ns) IH CLK_DELAY t – SHSKHOV Freescale Semiconductor Eqn. 10 Eqn. 11 Eqn. 12 ...

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... Note that the internal clock which is guaranteed to be 50% duty cycle is used to sample the data, and therefore used in the equations. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor < ...

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... DATA_DELAY SHSCK ODLY < – – < – DATA_DELAY OH SHSIXKH + t t < t – SHSIXKH INT_CLK_DLY CLK_DELAY + t DATA_DELAY < < 1.5 CLK_DELAY DATA_DELAY × < 1.5 t SHSCK t – SHSIVKH + t INT_CLK_DLY + t DATA_DELAY × – – SHSCK ODLY SHSIVKH Freescale Semiconductor Eqn. 15 Eqn. 16 Eqn. 17 Eqn. 18 Eqn. 19 ...

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... JTAG external clock rise and fall times TRST assert time Input setup times: Boundary-scan data Input hold times: Boundary-scan data Valid times: Boundary-scan data Output hold times: Boundary-scan data MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Symbol Condition V — — — ...

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... JTG . TCLK . TCLK = 50 Ω JTKHKL t JTG VM = Midpoint Voltage (OVDD/ TRST VM = Midpoint Voltage (OVDD/2) Figure 34. TRST Timing Diagram 1 (continued) Min Max Unit the midpoint of the signal in question. TCLK Figure symbolizes JTAG JTDVKH clock JTG OVDD Ω JTGR t JTGF VM Freescale Semiconductor Notes 5 17). ...

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... JTAG External Clock TDI, TMS t JTKLOX TDO TDO Output Data Valid Figure 36. Test Access Port Timing Diagram MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor VM t JTDVKH t JTKLDV t JTKLDZ VM = Midpoint Voltage (OVDD/2) Figure 35. Boundary-Scan Timing Diagram VM ...

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... 0.1 × C 250 — μA — ± Min Max Unit 0 400 kHz μs 1.3 — μs 0.6 — μs 0.6 — μs 0.6 — 100 — ns Freescale Semiconductor Notes — — — 4 Notes — — — — — — ...

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... Figure 37 provides the AC test load for the I Output Figure 38 shows the AC timing diagram for the I SDA t I2CF t I2CL SCL t I2SXKL S MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Electrical Specifications (continued) Table 46). Symbol t I2DXKL CBUS compatible masters bus devices t I2PVKH t ...

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... V ≤ V ≤ symbol referenced in Table IN , VIH = 0.7 × Symbol Min t PCKHOV t PCKHOX t PCKHOZ t PCIVKH Min Max 0.5 × 0 0.3 × OV –0.5 DD 0.9 × OV — DD 0.1 × OV — DD — ± Max Unit — 6 — ns — 3.0 — ns Freescale Semiconductor Unit μA Notes ...

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... Input timings are measured at the pin. 5 PCI specifications allows 2 ns skew for 33 MHz but includes the total allowed skew, board, connectors, etc. 6 Value does not comply with the PCI 2.3 Local Bus Specifications. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor , VIH = 0.7 × ...

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... This section describes the DC and AC electrical specifications for the serial ATA (SATA) of the MPC8379E. Note that the external cabled applications or long backplane applications (Gen1x and Gen2x) are not supported. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev Ω Ω Figure 39. PCI AC Test Load t PCIVKH t PCIXKH t PCKHOV t PCKHOX t PCKHOZ OVDD/2 Freescale Semiconductor ...

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... SATA reference clock timing waveform. Ref_CLK Figure 42. SATA Reference Clock Timing Waveform 15.2 Transmitter (Tx) Output Characteristics This section discusses the Gen1i/1.5G and Gen2i/3G transmitter output characteristics for the SATA interface. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Table Condition Symbol Min — t CLK_REF — ...

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... Typical Max Units 1.5 — Gbps 666.667 670.2333 ps — 0.355 UI p-p — 0.47 UI p-p — 0.175 UI p-p — 0.22 UI p-p Typical Max Units 550 700 mV p-p Ω 100 115 Freescale Semiconductor Notes 1 — Notes — — Notes 1 — ...

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... Gen1i or 1.5 Gbits/s differential receiver input DC characteristics for the SATA interface. Table 56. Gen1i/1.5G Receiver Input DC Specifications Parameter Differential input voltage Differential Rx input impedance Note: 1 Voltage relative to common of either signal comprising a differential pair. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Symbol Min t — CH_SPEED T 333 — ...

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... UI p-p — 0.35 UI p-p Typical Max Units 500 750 mVp-p Ω 100 115 Typical Max Units 3.0 — Gbps 333.33 335.11 ps — 0.46 UI p-p — 0.60 UI p-p — 0.65 UI p-p Freescale Semiconductor Notes — Notes 1 — Notes — — ...

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... Timers inputs and outputs are asynchronous to any visible clock. Timers outputs should be synchronized before use by any external synchronous logic. Timers inputs are required to be valid for at least t MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Symbol Min U — ...

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... R L Figure 43. Timers AC Test Load Condition Symbol I = – — — ≤ V ≤ PIWID OVDD/2 Min Max 2.4 — — 0.5 — 0.4 2 0.3 DD –0.3 0.8 — ± 30 Symbol Min Unit PIWID ns to ensure proper operation. Freescale Semiconductor Unit μA ...

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... IPIC inputs are required to be valid for at least t in edge triggered mode. 19 SPI This section describes the DC and AC electrical specifications for the SPI of the MPC8379E. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor = 50 Ω Figure 44. GPIO AC Test Load Table 64 ...

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... Symbol Min Max t 0.5 6 NIKHOV NEKHOV t 4 — NIIVKH t 0 — NIIXKH t 4 — NEIVKH t 2 — NEIXKH symbolizes the internal NIKHOV OVDD Ω 67. Note that although the specifications Freescale Semiconductor Unit V V μ Unit for ...

Page 69

... For illustration purpose, only one SerDes lane is used for description. The figure shows waveform for either a transmitter output (SDn_TX and SDn_TX receiver input (SDn_RX and SDn_RX). Each signal swings between A volts and B volts where A > B. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor tN EIXKH t ...

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... SDn_RX. DIFFp = |A B| volts. – DIFFp DIFFp × Figure ÷ ÷ 2, which is the arithmetic mean of the two SDn_TX , is defined as the difference The V value can be either positive defined as the difference of the two ID value can be either positive example for differential waveform. Freescale Semiconductor ...

Page 71

... SGND_SRDSn (xcorevss) followed by on-chip AC-coupling. — The external reference clock driver must be able to drive this termination. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Differential Swing, VID or VOD = A – B Differential Peak Voltage, VDIFFp = |A – B| Differential Peak-Peak Voltage, VDIFFpp = 2 × VDIFFp (not shown) is 500 mV in one phase and – ...

Page 72

... The input amplitude of the differential clock must be between 400 mV and 1600 mV differential peak-peak (or between 200 mV and 800 mV differential peak). In other words, each signal wire of the differential pair must have a single-ended swing less than 800 mV and MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev Ω Input Amp 50 Ω Freescale Semiconductor ...

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... SDn_REF_CLK SDn_REF_CLK Figure 50. Differential Reference Clock Input DC Requirements (External DC-Coupled) MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor the maximum average current requirements sets the Figure 51 200 mV < Input Amplitude or Differential Peak < 800 mV High-Speed Serial Interfaces (HSSI) Section 20.2.1, “ ...

Page 74

... AC-coupling. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev 400 mV < SDn_REF_CLK Input Amplitude < 800 mV 150 fdafdV < 400 mV max cm V < 400 mV max cm Vcm V > V – 400m V min Freescale Semiconductor ...

Page 75

... They might also vary from one vendor to the other. Therefore, Freescale Semiconductor can neither provide the optimal clock driver reference circuits, nor guarantee the correctness of the following clock driver connection reference circuits. The system designer is recommended ...

Page 76

... LVPECL output’s differential peak is 900 mV and the desired SerDes reference clock input amplitude is selected as 600 mV, the attenuation factor is 0.67, which requires Ω. Please consult MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev SDn_REF_CLK 100 Ω differential PWB trace SDn_REF_CLK MPC8379E Ω 50 SerDes Refer. CLK Receiver 50 Ω Figure 55 assumes Freescale Semiconductor ...

Page 77

... Phase noise less than 100 KHz can be tracked by the PLL and data recovery loops and is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor SDn_REF_CLK 100 Ω ...

Page 78

... Rise Edge Rate Fall Edge Rate Rise-Fall Matching Figure 57. Figure 58. SDn_REF_CLK V +100 mV CROSS MEDIAN V CROSS MEDIAN V –100 mV CROSS MEDIAN SDn_REF_CLK Min Max Unit Notes 1.0 4.0 V/ 1.0 4.0 V/ 200 — — –200 mV 2 — Fall Edge Rate T T FALL RISE Freescale Semiconductor ...

Page 79

... The package parameters are provided in the following list. The package type × 31 mm, 689 plastic ball grid array (TePBGA II). Package outline Interconnects Pitch Module height (typical) Solder Balls Ball diameter (typical) MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor SD1_RXn or SD1_TXn or SD2_RXn SD2_TXn 50 Ω 50 Ω SD1_TXn or SD1_RXn or ...

Page 80

... Dimensioning and tolerancing per ASME Y14. 5M-1994. 3 Maximum solder ball diameter measured parallel to Datum A. 4 Datum A, the seating plane, is determined by the spherical crowns of the solder balls. 5 Parallelism measurement should exclude any effect of mark on top surface of package. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev Freescale Semiconductor ...

Page 81

... MA7 MA8 MA9 MA10 MA11 MA12 MA13 MA14 MBA0 MBA1 MBA2 MCAS_B MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Table 69. TePBGA II Pinout Listing Package Pin Number Clock Signals K24 C10 N24 L24 M24 M25 M26 L26 AF11 DDR SDRAM Memory Interface ...

Page 82

... GVDD — O GVDD — O GVDD — O GVDD — I/O GVDD 9 I/O GVDD 9 O GVDD — O GVDD — O GVDD — O GVDD — O GVDD — O GVDD — O GVDD — O GVDD — O GVDD — I/O GVDD 11 I/O GVDD 11 I/O GVDD 11 I/O GVDD 11 Freescale Semiconductor ...

Page 83

... MDQ8 MDQ9 MDQ10 MDQ11 MDQ12 MDQ13 MDQ14 MDQ15 MDQ16 MDQ17 MDQ18 MDQ19 MDQ20 MDQ21 MDQ22 MDQ23 MDQ24 MDQ25 MDQ26 MDQ27 MDQ28 MDQ29 MDQ30 MDQ31 MDQ32 MDQ33 MDQ34 MDQ35 MDQ36 MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number ...

Page 84

... GVDD 11 I/O GVDD 11 I/O GVDD 11 I/O GVDD 11 I/O GVDD 11 I/O GVDD 11 I/O GVDD 11 I/O GVDD 11 I/O GVDD 11 I/O GVDD 11 I/O GVDD 11 I/O GVDD 11 I/O GVDD 11 I/O GVDD 11 I/O GVDD 11 I/O GVDD 11 I/O GVDD 11 I/O GVDD 11 I/O GVDD 11 I/O GVDD 11 Freescale Semiconductor ...

Page 85

... MODT0 MODT1 MODT2 MODT3 MRAS_B MVREF1 MVREF2 MWE_B UART_SIN1/ MSRCID2/LSRCID2 UART_SOUT1/ MSRCID0/LSRCID0 UART_CTS_B[1]/ MSRCID4/LSRCID4 UART_RTS_B1 UART_SIN2/ MSRCID3/LSRCID3 UART_SOUT2/ MSRCID1/LSRCID1 UART_CTS_B[2]/ MDVAL/LDVAL UART_RTS_B[2] MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number AH1 AJ3 AA3 DUART Interface L28 L27 ...

Page 86

... I/O LBVDD — I/O LBVDD — I/O LBVDD — I/O LBVDD — I/O LBVDD — I/O LBVDD — I/O LBVDD — I/O LBVDD — I/O LBVDD — I/O LBVDD — I/O LBVDD — I/O LBVDD — O LBVDD — Freescale Semiconductor ...

Page 87

... LFCLE/LGPL0 LFALE/LGPL1 LFRE_B/LGPL2/LOE_B LFWP_B/LGPL3 LGPL4/LFRB_B/LGTA_B/ LUPWAIT/LPBSE LA9/LGPL5 LSYNC_IN LSYNC_OUT LWE_B0/LFWE0/LBS_B0 LWE_B1/LFWE1/LBS_B1 LWE_B2/LFWE2/LBS_B2 LWE_B3/LFWE3/LBS_B3 TSEC1_COL/GPIO2[20] TSEC1_CRS/GPIO2[21] MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number C29 E28 B26 J25 H29 A22 B22 C23 B23 D25 F19 C27 D24 C24 ...

Page 88

... LVDD1 17 I LVDD1 17 O LVDD1 17 I/O LVDD1 17 I/O LVDD1 17 I/O LVDD1 17 I/O LVDD1 17 I/O LVDD1 17 I LVDD1 17 I/O LVDD1 17 I/O LVDD1 17 I/O LVDD2 17 I/O LVDD2 17 O LVDD2 17 I LVDD2 17 I/O LVDD2 17 I/O LVDD2 17 I/O LVDD2 17 I/O LVDD2 17 I/O LVDD2 17 Freescale Semiconductor ...

Page 89

... GPIO1[6]/GTM1_TIN3/ GTM2_TIN4/DREQ2_B GPIO1[7]/GTM1_TGATE3_B/ GTM2_TGATE4_B/DACK2_B GPIO1[8]/GTM1_TOUT3_B/ DDONE2_B GPIO1[9]/GTM1_TIN4/ GTM2_TIN3/DREQ3_B GPIO1[10]/GTM1_TGATE4_B/ GTM2_TGATE3_B/DACK3_B GPIO1[11]/GTM1_TOUT4_B/ GTM2_TOUT3_B/DDONE3_B MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number AH25 AG28 AJ26 AG26 AH28 AF27 AJ28 AF29 GPIO1 Interface P25 N25 ...

Page 90

... I/O OVDD — I/O OVDD — I/O OVDD — I/O OVDD — I/O OVDD — I/O OVDD — I/O OVDD — I/O OVDD 2 I/O OVDD 2 I/O OVDD 2 I/O OVDD 2 I OVDD — I OVDD 4 O OVDD 3 I OVDD 4 I OVDD 4 Freescale Semiconductor ...

Page 91

... PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number PCI Signals P26 N28 P29 P27 R26 R29 T24 T25 R27 P28 U25 R28 U26 ...

Page 92

... OVDD 5 O OVDD 2 I/O OVDD 5 I/O OVDD — I/O OVDD 5 I/O OVDD — I OVDD — I OVDD — I OVDD — I OVDD — O OVDD — I/O OVDD 5 I/O OVDD 5 I/O OVDD 5 I OVDD — O OVDD 2 I/O OVDD — I/O OVDD — Freescale Semiconductor ...

Page 93

... L1_SD_RXE_N L1_SD_RXE_P L1_SD_TXA_N L1_SD_TXA_P L1_SD_TXE_N L1_SD_TXE_P L1_SDAVDD_0 L1_SDAVSS_0 L1_XCOREVDD L1_XCOREVSS AG14, AG15, AG16, AH16, AG18, AG20 L1_XPADVDD MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number F10 D9 C9 AE10 AD10 AD9 PMC Interface D13 SerDes1 Interface AJ14 AG19 ...

Page 94

... SerDes Core — GND SerDes I/O — Power (1.0 or 1.05 V) SerDes I/O — GND I/O OVDD I/O OVDD I/O OVDD I OVDD Freescale Semiconductor — — — — — — — — — — — — — — — — — — ...

Page 95

... W18, L19, M19, N19, P19, T19, U19, V19, W19, AC20, G21, AF21, C22, J23, AA23, AJ23, B24, W24, AF24, K25, R25, AD25, D26, G27, M27, T27, Y27, AB27, AG27, A29, MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Package Pin Number AD12 AE12 AE14 ...

Page 96

... Standard C11 No Connect F16, F17, AD16, AD17 Pull Down B16, AH18 Table 3. Pin Type Power Supply Notes — or 1.05 V) — 1.05 V) Power for — system PLL GVDD SDRAM I/O 1.8 V) OVDD (3.3 V) — — — — Freescale Semiconductor — — ...

Page 97

... PCI agent devices in the system, to allow the device to function. When the device is configured as a PCI agent device, PCI_CLK is the primary input clock. When the device is configured as a PCI agent device the CLKIN signal should be tied to GND. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor e300 core core_clk Core PLL ...

Page 98

... Table 70. Configurable Clock Units Default Frequency csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 csb_clk Off, csb_clk csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 Eqn. 20 Eqn. 21 Eqn. 22 Options Freescale Semiconductor ...

Page 99

... VCO frequency = 2 × (CSB frequency) × (System PLL VCO Divider). The VCO divider needs to be set properly so that the System PLL VCO frequency is in the range of 400–800 MHz. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Minimum Operating 1 Frequency (MHz) ...

Page 100

... Input Clock Ratio System PLL Multiplication Factor Reserved Reserved × 2 × 3 × 4 × 5 × 6 × × 15 Table 73. VCO Division Factor Input Clock Frequency (MHz) 25 33.33 csb_clk Frequency (MHz) 133 167 150 200 Freescale Semiconductor Table 74 2 66.67 133 200 267 333 400 ...

Page 101

... Low 1000 Low 1001 Low 1010 Low 1011 Low 1100 Low 1101 Low 1110 Low 1111 MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Input Clock Frequency (MHz) csb_clk : 25 2 Input Clock Ratio 175 200 225 250 275 300 ...

Page 102

... Ratio 6 0 PLL bypassed (PLL off, csb_clk clocks core directly) n n/a 0 1:1 0 1:1 0 1:1 1 1.5:1 1 1.5:1 1 1.5:1 0 2:1 0 2:1 0 2:1 1 2.5:1 1 2.5:1 1 2.5:1 0 3:1 0 3:1 0 3:1 1 3.5:1 1 3.5:1 1 3.5:1 1 VCO Divider PLL bypassed (PLL off, csb_clk clocks core directly) n Freescale Semiconductor ...

Page 103

... CSB frequencies less than 133 MHz will not support Gigabit Ethernet rates. 4 Minimum data rate for DDR2 is 250 MHz and for DDR1 is 167 MHz. 5 Applies to DDR2 only. 6 Applies to eLBC PLL-enabled mode only. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor core_clk : csb_clk Ratio 6 0 4:1 0 4:1 0 ...

Page 104

... MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 104 × where I/O I/O , can be obtained from the equation: J × Symbol Value Unit °C θJA °C θJA °C θJMA °C θJMA °C θJB °C θJC ψ °C the power dissipation of the I/O drivers. Freescale Semiconductor Notes ...

Page 105

... where junction temperature (° thermocouple temperature on top of package (°C) T MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor – J NOTE × NOTE Ψ determine the junction temperature and a measure of the JT × are possible ...

Page 106

... Because of the wide variety of application environments, a single standard heat sink applicable to all cannot be specified. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 106 θ For instance, the user can change the size of the heat θ CA Freescale Semiconductor ...

Page 107

... Heat sink vendors include the following: Aavid Thermalloy www.aavidthermalloy.com Alpha Novatech www.alphanovatech.com International Electronic Research Corporation (IERC) www.ctscorp.com Millennium Electronics (MEI) www.mei-thermal.com MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Thermal Resistance Air Flow Natural Convection 0.5 m/s 1 m/s 2 m/s 4 m/s Natural Convection 0.5 m/s ...

Page 108

... From this case temperature, the junction temperature is determined from the junction to case thermal resistance θ where junction temperature (° case temperature of the package (°C) C MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 108 × Freescale Semiconductor ...

Page 109

... PCB, utilizing short traces to minimize inductance. Capacitors may be placed directly under the device using a standard escape pattern. Others may surround the part. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor , and preferably these voltages will be derived directly from V DD ...

Page 110

... MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 110 2 C). is trimmed until the voltage at the pad equals P )/2. N OVDD R N Pad Data R P OGND Figure 63. Driver Impedance Measurement /2 (see Figure 63). The DD and R are designed to be close to each P N SW2 SW1 Freescale Semiconductor ...

Page 111

... For more information on required pull-up resistors and the connections required for the JTAG interface, see AN3665, “MPC837xE Design Checklist.” 25 Ordering Information Ordering information for the parts fully covered by this specification document is provided in Section 25.1, “Part Numbers Fully Addressed by This Document.” MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor × source source )) × ...

Page 112

... DDR Revision 3 Frequency Data Rate Level AN = 800 MHz G = 400 MHz Contact local AL = 667 MHz F = 333 MHz Freescale AJ = 533 MHz D = 266 MHz sales office AG = 400 MHz MPC8379E 800 MHz/400 MHz 667 MHz/400 MHz 533 MHz/333 MHz 400 MHz/266 MHz Freescale Semiconductor ...

Page 113

... TePBGA II MPC8378E MPC8379 MPC8379E 25.2 Part Marking Parts are marked as in the example shown in Figure 64. Freescale Part Marking for TePBGA II Devices MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor SVR Rev 1.0 Rev. 2.1 0x80C7_0010 0x80C7_0021 0x80C6_0010 0x80C6_0021 0x80C5_0010 0x80C5_0021 ...

Page 114

... Characteristics,” and Table removed “Ethernet Management MDIO pin” from list min value to 1.7. IH LBKHLR and in Section 22, “Clocking,” updated LCCR 35, “USB General Timing Parameters (ULPI Table 40, “Local Bus , LBOTOT1 LBOTOT2 LBOTOT3 Table 75, “CSB Frequency Options for Agent Freescale Semiconductor . . ...

Page 115

... In Table 82, “Available Parts (Core/DDR Data Rate),” added new row for 800/400 MHz. 0 12/2008 Initial public release. MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor Substantive Change(s) = 65°C (W)”. j ,” updated I REF Listing,” ...

Page 116

... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...