MPC8379EVRAJF Freescale Semiconductor, MPC8379EVRAJF Datasheet - Page 77
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MPC8379EVRAJF
Manufacturer Part Number
MPC8379EVRAJF
Description
MPU PWRQUICC II 533MHZ 689TEPBGA
Manufacturer
Freescale Semiconductor
Series
PowerQUICC II PROr
Datasheets
1.MPC8377EVRAGD.pdf
(126 pages)
2.MPC8377EVRAGD.pdf
(2 pages)
3.MPC8379VRAGD.pdf
(116 pages)
Specifications of MPC8379EVRAJF
Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
533MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
689-TePBGA II
Maximum Clock Frequency
533 MHz
Operating Supply Voltage
1.8 V to 2.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
I/o Voltage
1.8 V, 2.5 V, 3.3 V
Minimum Operating Temperature
0 C
Core Size
32 Bit
Program Memory Size
64KB
Cpu Speed
533MHz
Embedded Interface Type
DUART, HSSI, I2C, IPIC, JTAG, SPI, USB
Digital Ic Case Style
BGA
No. Of Pins
689
Rohs Compliant
Yes
For Use With
MPC8377E-RDBA - BOARD REF DES MPC8377 REV 2.1MPC8377E-MDS-PB - BOARD MODULAR DEV SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8379EVRAJF
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MPC8379EVRAJF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
clock driver chip manufacturer to verify whether this connection scheme is compatible with a particular
clock driver chip.
Figure 56
It assumes the DC levels of the clock driver are compatible with device SerDes reference clock input’s DC
requirement.
20.2.4
The clock driver selected should provide a high quality reference clock with low phase noise and
cycle-to-cycle jitter. Phase noise less than 100 KHz can be tracked by the PLL and data recovery loops and
is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise
Freescale Semiconductor
LVPECL CLK Driver Chip
Clock Driver
Single-Ended CLK
Driver Chip
Clock Driver
Clock Driver
Figure 55. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)
shows the SerDes reference clock connection reference circuits for a single-ended clock driver.
AC Requirements for SerDes Reference Clocks
CLK_Out
CLK_Out
CLK_Out
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Figure 56. Single-Ended Connection (Reference Only)
33 Ω
R1
R1
100 Ω differential PWB trace
Total 50 Ω. Assume clock driver’s
output impedance is about 16 Ω.
R2
R2
50 Ω
100 Ω differential PWB trace
10 nF
10 nF
SDn_REF_CLK
SDn_REF_CLK
SDn_REF_CLK
SDn_REF_CLK
50 Ω
50 Ω
High-Speed Serial Interfaces (HSSI)
50 Ω
50 Ω
MPC8379E
MPC8379E
SerDes Refer.
CLK Receiver
SerDes Refer.
CLK Receiver
77