MPC8379EVRAJF Freescale Semiconductor, MPC8379EVRAJF Datasheet - Page 48

• Manufacturer Part Number: MPC8379EVRAJF
• Description: MPU PWRQUICC II 533MHZ 689TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8379EVRAJF

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 533MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 689-TePBGA II
• Maximum Clock Frequency: 533 MHz
• Operating Supply Voltage: 1.8 V to 2.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 533MHz
• Embedded Interface Type: DUART, HSSI, I2C, IPIC, JTAG, SPI, USB
• Digital Ic Case Style: BGA
• No. Of Pins: 689
• Rohs Compliant: Yes
• For Use With: MPC8377E-RDBA - BOARD REF DES MPC8377 REV 2.1MPC8377E-MDS-PB - BOARD MODULAR DEV SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Secure Digital Host Controller (eSDHC)
11.2.2.2
There is no minimum delay constraint due to the full clock cycle between the driving and sampling of data.
This means that Data + Clock delay must be greater than –2 ns. This is always fulfilled.
11.3
Table 43
Figure
48
At recommended operating conditions OV
SD_CLK clock frequency—high speed mode
SD_CLK clock cycle
SD_CLK clock frequency—identification mode
SD_CLK clock low time
SD_CLK clock high time
SD_CLK clock rise and fall times
Input setup times: SD_CMD, SD_DATx, SD_CD to
SD_CLK
Input hold times: SD_CMD, SD_DATx, SD_CD to SD_CLK
Output delay time: SD_CLK to SD_CMD, SD_DATx valid
Output Hold time: SD_CLK to SD_CMD, SD_DATx invalid
SD_CLK delay within device
SD Card Input Setup
SD Card Input Hold
SD Card Output Valid
31.
provides the eSDHC AC timing specifications for high-speed mode as defined in
eSDHC AC Timing Specifications (High-Speed Mode)
Full-Speed Read Meeting Hold (Minimum Delay)
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Parameter
Table 43. eSDHC AC Timing Specifications for High-Speed Mode
t
CLK_DELAY
DD
= 3.3 V ± 165 mV.
+ t
OH
+ t
DATA_DELAY
t
INT_CLK_DLY
t
Symbol
t
t
t
t
t
t
SHSKHOV
SHSKHOX
t
SHSCKR/
SHSIVKH
SHSIXKH
f
SHSCKH
SHSCKF
t
SHSCKL
f
SHSCK
SFSCK
t
SIDCK
ODLY
t
ISU
t
IH
1
> t
SFSIXKH
Min
1.5
20
—
—
—
0
0
7
7
5
0
0
6
2
Max
400
50
14
—
—
—
—
—
—
—
—
—
3
4
Freescale Semiconductor
MHz
Unit
KHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 30
Notes
Eqn. 9
—
—
—
2
2
2
2
2
2
2
4
3
3
3
and