MPC8379EVRAJF Freescale Semiconductor, MPC8379EVRAJF Datasheet - Page 61

• Manufacturer Part Number: MPC8379EVRAJF
• Description: MPU PWRQUICC II 533MHZ 689TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8379EVRAJF

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 533MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 689-TePBGA II
• Maximum Clock Frequency: 533 MHz
• Operating Supply Voltage: 1.8 V to 2.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 533MHz
• Embedded Interface Type: DUART, HSSI, I2C, IPIC, JTAG, SPI, USB
• Digital Ic Case Style: BGA
• No. Of Pins: 689
• Rohs Compliant: Yes
• For Use With: MPC8377E-RDBA - BOARD REF DES MPC8377 REV 2.1MPC8377E-MDS-PB - BOARD MODULAR DEV SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.1
The reference clock is a single ended input clock required for the SATA interface operation. The AC
requirements for the SATA reference clock are listed in the
Figure 42
15.2
This section discusses the Gen1i/1.5G and Gen2i/3G transmitter output characteristics for the SATA
interface.
Freescale Semiconductor
SD_REF_CLK/ SD_REF_CLK
frequency range
SD_REF_CLK/ SD_REF_CLK
clock frequency tolerance
SD_REF_CLK/ SD_REF_CLK
reference clock duty cycle
SD_REF_CLK/ SD_REF_CLK
cycle to cycle Clock jitter (period
jitter)
SD_REF_CLK/ SD_REF_CLK total
reference clock jitter, phase jitter
(peak-peak)
Note:
1
2
3
Only 100/125/150 MHz have been tested, other in between values will not work correctly with the rest of the system.
In a frequency band from 150 kHz to 15 MHz at BER of 10
Total peak to peak Deterministic Jitter "D
Requirements for SATA REF_CLK
Transmitter (Tx) Output Characteristics
shows the SATA reference clock timing waveform.
Parameter
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Ref_CLK
Table 51. SATA Reference Clock Input Requirements
Figure 42. SATA Reference Clock Timing Waveform
Peak-to-peak jitter
Measured at 1.6V
Cycle-to-cycle at
at ref clock input
ref clock input
Condition
J
" should be less than or equal to 50 ps.
—
—
t
t
CLK_DUTY
t
Symbol
CLK_REF
CLK_TOL
t
t
CLK_CJ
CLK_PJ
-12
.
T
L
Table
–350
Min
–50
40
—
—
51.
T
H
100/125/150
Typical
—
—
50
0
+350
Max
100
+50
—
60
Serial ATA (SATA)
MHz
Unit
ppm
ps
ps
%
Notes
2, 3
—
—
—
1
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