MPC8379EVRAJF Freescale Semiconductor, MPC8379EVRAJF Datasheet - Page 100

MPU PWRQUICC II 533MHZ 689TEPBGA

MPC8379EVRAJF

Manufacturer Part Number
MPC8379EVRAJF
Description
MPU PWRQUICC II 533MHZ 689TEPBGA
Manufacturer
Freescale Semiconductor
Series
PowerQUICC II PROr
Datasheets

Specifications of MPC8379EVRAJF

Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
533MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
689-TePBGA II
Maximum Clock Frequency
533 MHz
Operating Supply Voltage
1.8 V to 2.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
I/o Voltage
1.8 V, 2.5 V, 3.3 V
Minimum Operating Temperature
0 C
Core Size
32 Bit
Program Memory Size
64KB
Cpu Speed
533MHz
Embedded Interface Type
DUART, HSSI, I2C, IPIC, JTAG, SPI, USB
Digital Ic Case Style
BGA
No. Of Pins
689
Rohs Compliant
Yes
For Use With
MPC8377E-RDBA - BOARD REF DES MPC8377 REV 2.1MPC8377E-MDS-PB - BOARD MODULAR DEV SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8379EVRAJF
Manufacturer:
Freescale Semiconductor
Quantity:
135
Part Number:
MPC8379EVRAJF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Clocking
As described in
configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the
primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk).
and
CLKIN/PCI_SYNC_IN ratios.
The RCWLR[SVCOD] denotes the system PLL VCO internal frequency as shown in
100
CFG_CLKIN_DIV
Table 75
at Reset
High
High
High
High
High
show the expected frequency values for the CSB frequency for select csb_clk to
1
Section 22, “Clocking,”
RCWLR[SVCOD]
RCWLR[SPMF]
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
0111–1111
0000
0001
0010
0011
0100
0101
0110
00
01
10
11
SPMF
0010
0011
0100
0101
0110
Table 74. CSB Frequency Options for Host Mode
Table 72. System PLL Multiplication Factors
Table 73. System PLL VCO Divider
The LBIUCM, DDRCM, and SPMF parameters in the reset
Input Clock Ratio
csb_clk :
2 : 1
3 : 1
4 : 1
5 : 1
6 : 1
2
System PLL Multiplication Factor
150
25
VCO Division Factor
Input Clock Frequency (MHz)
csb_clk Frequency (MHz)
× 7 to × 15
Reserved
Reserved
× 2
× 3
× 4
× 5
× 6
4
8
2
1
33.33
133
167
200
Freescale Semiconductor
Table
73.
66.67
Table 74
2
133
200
267
333
400

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