MPC8379EVRAJF Freescale Semiconductor, MPC8379EVRAJF Datasheet - Page 20
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MPC8379EVRAJF
Manufacturer Part Number
MPC8379EVRAJF
Description
MPU PWRQUICC II 533MHZ 689TEPBGA
Manufacturer
Freescale Semiconductor
Series
PowerQUICC II PROr
Datasheets
1.MPC8377EVRAGD.pdf
(126 pages)
2.MPC8377EVRAGD.pdf
(2 pages)
3.MPC8379VRAGD.pdf
(116 pages)
Specifications of MPC8379EVRAJF
Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
533MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
689-TePBGA II
Maximum Clock Frequency
533 MHz
Operating Supply Voltage
1.8 V to 2.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
I/o Voltage
1.8 V, 2.5 V, 3.3 V
Minimum Operating Temperature
0 C
Core Size
32 Bit
Program Memory Size
64KB
Cpu Speed
533MHz
Embedded Interface Type
DUART, HSSI, I2C, IPIC, JTAG, SPI, USB
Digital Ic Case Style
BGA
No. Of Pins
689
Rohs Compliant
Yes
For Use With
MPC8377E-RDBA - BOARD REF DES MPC8377 REV 2.1MPC8377E-MDS-PB - BOARD MODULAR DEV SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8379EVRAJF
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MPC8379EVRAJF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
DDR1 and DDR2 SDRAM
The minimum frequency for DDR2 is 250 MHz data rate (125 MHz clock), 167 MHz data rate (83 MHz
clock) for DDR1.
20
MDQ//MDM output setup with respect to MDQS
MDQ//MDM output hold with respect to MDQS
MDQS preamble start
MDQS epilogue end
Note:
1
2
3
4
5
6
7
8
The symbols used for timing specifications follow the pattern of t
inputs and t
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
t
(A) are setup (S) or output valid time. Also, t
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ//MDM/MDQS.
Note that t
from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). t
of the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in
the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same
adjustment value. See the MPC8379E PowerQUICC II Pro Host Processor Reference Manual for a description and
understanding of the timing modifications enabled by use of these bits.
Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data MDQ, ECC, or
data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
All outputs are referenced to the rising edge of MCKn at the pins of the microprocessor. Note that t
conventions described in Note 1.
Clock Control register is set to adjust the memory clocks by 1/2 the applied cycle.
See AN3665, “MPC837xE Design Checklist,” for proper DDR termination.
DDKHAS
symbolizes DDR timing (DD) for the time t
DDKHMH
(first two letters of functional block)(reference)(state)(signal)(state)
Table 21. DDR1 and DDR2 SDRAM Output AC Timing Specifications (continued)
Parameter
follows the symbol conventions described in Note 1. For example, t
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
400 MHz data rate
333 MHz data rate
266 MHz data rate
200 MHz data rate
400 MHz data rate
333 MHz data rate
266 MHz data rate
200 MHz data rate
DDKLDX
Symbol
t
t
MCK
t
t
t
t
DDKHDS,
DDKHDX,
DDKHMP
DDKHME
DDKLDS
DDKLDX
symbolizes DDR timing (DD) for the time t
memory clock reference (K) goes from the high (H) state until outputs
1
–0.5 × t
(first two letters of functional block)(signal)(state) (reference)(state)
for outputs. Output hold time can be read as DDR timing
1100
1200
1100
1200
–0.6
Min
550
800
700
800
MCK
–0.6
DDKHMH
DDKHMH
–0.5 × t
can be modified through control
Max
0.6
describes the DDR timing (DD)
—
—
—
—
—
—
—
—
MCK
MCK
DDKHMP
+ 0.6
memory clock reference
Freescale Semiconductor
follows the symbol
Unit
ps
ps
ns
ns
Notes
5, 8
5, 8
6, 8
6, 8
for