XPC8240LZU200E Freescale Semiconductor, XPC8240LZU200E Datasheet - Page 13

• Manufacturer Part Number: XPC8240LZU200E
• Description: MCU HOST PROCESSOR 352-TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC IIr

Specifications of XPC8240LZU200E

• Processor Type: MPC82xx PowerQUICC II 32-bit
• Speed: 200MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 352-TBGA
• Core Size: 32 Bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Embedded Interface Type: I2C
• Digital Ic Case Style: TBGA
• No. Of Pins: 352
• Supply Voltage Range: 2.5V To 2.75V
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Figure 6 shows the PCI_SYNC_IN input clock timing diagram, and Figure 7 shows the DLL locking range
loop delay versus frequency of operation.
MPC8240 Integrated Processor Hardware Specifications
At recommended operating conditions (see Table 2) with LV
Notes:
1. These specifications are for the default driver strengths indicated in Table 4.
2. Rise and fall times for the PCI_SYNC_IN input are measured from 0.4 to 2.4 V.
3. Specification value at maximum frequency of operation.
4. Relock time is guaranteed by design and characterization. Relock time is not tested.
5. Rise and fall times for the OSC_IN input are guaranteed by design and characterization. OSC_IN input rise and fall
6. Relock timing is guaranteed by design. PLL-relock time is the maximum amount of time required for PLL lock after
7. DLL_STANDARD is bit 7 of the PMC2 register <72>. N is a non-zero integer (1 or 2). T
8. Pin-to-pin skew includes quantifying the additional amount of clock skew (or jitter) from the DLL besides any
Num
16
17
18
19
20
21
22
23
times are not tested.
a stable V
PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRST_CPU/HRST_CTRL
must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the reset sequence.
SDRAM_SYNC_OUT clock cycle in ns. t
board runner) from SDRAM_SYNC_OUT to SDRAM_SYNC_IN in ns; 6.25 inches of loop length (unloaded PC
board runner) corresponds to approximately 1 ns of delay. t
is at tap point 0 and the DLL is contributing no delay; t
ranges.
intentional skew added to the clocking signals from the variable length DLL synchronization feedback loop, that is,
the amount of variance between the internal sys_logic_clk and the SDRAM_SYNC_IN signal after the DLL is
locked. While pin to pin skew between SDRAM_CLKs can be measured, the relationship between the internal
sys_logic_clk and the external SDRAM_SYNC_IN cannot be measured and is guaranteed by design.
DLL lock range with DLL_STANDARD = 0 (default)
Frequency of operation (OSC_IN)
OSC_IN cycle time
OSC_IN rise and fall times
OSC_IN duty cycle measured at 1.4 V
OSC_IN frequency stability
OSC_IN V
OSC_IN V
PCI_SYNC_IN
DD
and PCI_SYNC_IN are reached during the reset sequence. This specification also applies when the
IH
IL
Characteristic and Condition
(loaded)
(loaded)
Table 7. Clock AC Timing Specifications (continued)
Figure 6. PCI_SYNC_IN Input Clock Timing Diagram
Freescale Semiconductor, Inc.
VM
For More Information On This Product,
5a
loop
Go to: www.freescale.com
VM = Midpoint Voltage (1.4 V)
1
VM
is the propagation delay of the DLL synchronization feedback loop (PC
5b
1
DD
= 3.3 V ± 0.3 V
fix0
equals approximately 3 ns. See Figure 7 for DLL3 locking
VM
fix0
is a fixed delay inherent in the design when the DLL
CV
0 ≤ (NT
IL
Min
Electrical and Thermal Characteristics
2.0
25
40
40
—
—
CV
clk
IH
– T
2
clk
≤
/2 – t
7
loop
Max
100
0.8
66
15
60
clk
5
– t
is the period of one
fix0
)
MHz
Unit
ppm
ns
ns
ns
%
V
V
3
Notes
7
5
13