XPC8240LZU200E Freescale Semiconductor, XPC8240LZU200E Datasheet - Page 21

• Manufacturer Part Number: XPC8240LZU200E
• Description: MCU HOST PROCESSOR 352-TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC IIr

Specifications of XPC8240LZU200E

• Processor Type: MPC82xx PowerQUICC II 32-bit
• Speed: 200MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 352-TBGA
• Core Size: 32 Bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Embedded Interface Type: I2C
• Digital Ic Case Style: TBGA
• No. Of Pins: 352
• Supply Voltage Range: 2.5V To 2.75V
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Table 13 provides the I
MPC8240 Integrated Processor Hardware Specifications
At recommended operating conditions (see Table 2) with LV
14, 15
16, 17, 3A, 3B, 3C, 3D 12288, 14336, 15360, 16384, 20480, 24576
18, 19
1A, 1B, 3E, 3F
1C, 1D
1E, 1F
Notes:
1. Values are in KHz, unless otherwise specified.
2. FDR Hex and Divider (Dec) values are listed in corresponding order.
3. Multiple Divider (Dec) values will generate the same input frequency, but each Divider (Dec) value will generate a
Num
1
2
3
4
5
6
7
8
unique output frequency as shown in Table 13.
FDR Hex
Start condition hold time
Clock low period
SCL/SDA rise time (from 0.5 to 2.4 V)
Data hold time
SCL/SDA fall time (from 2.4 to 0.5 V)
Clock high time
Data setup time (MPC8240 as a
master only)
Start condition setup time (for repeated
start condition only)
2
Characteristic
Table 12. MPC8240 Maximum I
9216, 10240
18432, 20480
24576, 28672, 30720, 32768
36864, 40960
49152, 61440
2
C output AC timing specifications for the MPC8240.
Freescale Semiconductor, Inc.
Table 13. I
For More Information On This Product,
Divider
2
Go to: www.freescale.com
C Output AC Timing Specifications
3
(FDR[5] == 0) × (D
D
(Dec)
FDR
(D
FDR
DD
4({FDR[5],FDR[1]} == b'10) –
3({FDR[5],FDR[1]} == b'11) –
2({FDR[5],FDR[1]} == b'00) –
+ (Output start condition hold time)
1({FDR[5],FDR[1]} == b'01))
8.0 + (16 × 2
= 3.3 V ± 0.3 V
/2) – (Output data hold time)
== 1) × (D
2
C Input Frequency (continued)
D
D
Min
FDR
FDR
FDR
—
—
FDR[4:2]
FDR
/2
/2
SDRAM_CLK
/16)/2N + (FDR[5]
/16)/2M
@ 33 MHz
Electrical and Thermal Characteristics
) × (5 –
21
16
10
Maximum I
8
5
4
SDRAM_CLK
2
@ 50 MHz
C Input Frequency
32
24
16
12
Max
8
6
< 5
—
—
—
—
—
—
—
CLKs
CLKs
CLKs
CLKs
CLKs
CLKs
Unit
SDRAM_CLK
ms
ns
@ 100 MHz
64
48
32
24
16
12
1
Notes
1, 2, 5
1, 2, 5
1, 2, 5
1, 2, 5
1, 2, 5
1, 5
3
4
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