XPC8240LZU200E Freescale Semiconductor, XPC8240LZU200E Datasheet - Page 18

• Manufacturer Part Number: XPC8240LZU200E
• Description: MCU HOST PROCESSOR 352-TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC IIr

Specifications of XPC8240LZU200E

• Processor Type: MPC82xx PowerQUICC II 32-bit
• Speed: 200MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 352-TBGA
• Core Size: 32 Bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Embedded Interface Type: I2C
• Digital Ic Case Style: TBGA
• No. Of Pins: 352
• Supply Voltage Range: 2.5V To 2.75V
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Electrical and Thermal Characteristics
Electrical and Thermal Characteristics
Table 10 describes the bit values for the PCI_HOLD_DEL values in PMCR2.
18
6–4 PCI_HOLD_DEL
Bit
Name
Table 10. Power Management Configuration Register 2 at 0x72
MPC8240 Integrated Processor Hardware Specifications
Reset
Value
xx0
Freescale Semiconductor, Inc.
For More Information On This Product,
PCI output hold delay values relative to PCI_SYNC_IN. The initial values of bits 6
and 5 are determined by the reset configuration pins MCP and CKE, respectively.
As these two pins have internal pull-up resistors, the default value after reset is
0b110.
Although the minimum hold times are guaranteed at shown values, changes in the
actual hold time can be made by incrementing or decrementing the value in these
bit fields of this register through software or hardware configuration. The increment
is in approximately 400-picosecond steps. Lowering the value in the 3-bit field
decreases the amount of output hold available.
000 For Silicon Rev. 1.0/1.1: 66-MHz PCI. Pull-down CKE configuration pin with a
001 Reserved
010 Reserved
011 Reserved
100 For Silicon Rev. 1.2/1.3: 66-MHz PCI. Pull-down CKE configuration pin with a
101 Reserved
110 For Silicon Rev. 1.2/1.3: 33-MHz PCI. This setting guarantees the minimum
111
2-k
(item 13a) and the maximum output valid (item 12a) times as specified in
Figure 9 are met for a 66-MHz PCI system. See Figure 12.
2-k
(item 13a) and the maximum output valid (item 12a) times as specified in
Figure 9 are met for a 66-MHz PCI system. See Figure 12.
For Silicon Rev. 1.0/1.1: 33-MHz PCI. This setting guarantees the minimum
output hold (item 13a) and the maximum output valid (item 12a) times as
specified in Figure 9 are met for a 33-MHz PCI system. See Figure 12.
output hold (item 13a) and the maximum output valid (item 12a) times as
specified in Figure 9 are met for a 33-MHz PCI system. See Figure 12.
(Default if reset configuration pins left unconnected.)
For Silicon Rev. 1.0/1.1: Default if reset configuration pins left unconnected.
Reserved
Ω
Ω
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or less value resistor. This setting guarantees the minimum output hold
or less value resistor. This setting guarantees the minimum output hold
Description