MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 2
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MPC8544VTALF
Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
Specifications of MPC8544VTALF
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
MPC8544E Overview
The e500 defines features that are not implemented on this device. It also generally defines some features
that this device implements more specifically. An understanding of these differences can be critical to
ensure proper operations.
2
•
•
•
— Double-precision floating-point APU. Provides an instruction set for double-precision (64-bit)
— 36-bit real addressing
— Embedded vector and scalar single-precision floating-point APUs. Provide an instruction set
— Memory management unit (MMU). Especially designed for embedded applications. Supports
— Enhanced hardware and software debug support
— Performance monitor facility that is similar to, but separate from, the device performance
256-Kbyte L2 cache/SRAM
— Flexible configuration
— Full ECC support on 64-bit boundary in both cache and SRAM modes
— Cache mode supports instruction caching, data caching, or both.
— External masters can force data to be allocated into the cache through programmed memory
— Eight-way set-associative cache organization (32-byte cache lines)
— Supports locking entire cache or selected lines. Individual line locks are set and cleared through
— Global locking and flash clearing done through writes to L2 configuration registers
— Instruction and data locks can be flash cleared separately.
— SRAM features include the following:
Address translation and mapping unit (ATMU)
— Eight local access windows define mapping within local 36-bit address space.
— Inbound and outbound ATMUs map to larger external address spaces.
DDR/DDR2 memory controller
— Programmable timing supporting DDR and DDR2 SDRAM
— 64-bit data interface
floating-point instructions that use the 64-bit GPRs.
for single-precision (32-bit) floating-point instructions.
4-Kbyte–4-Gbyte page sizes.
monitor
ranges or special transaction types (stashing).
– 1, 2, or 4 ways can be configured for stashing only.
Book E instructions or by externally mastered transactions.
– I/O devices access SRAM regions by marking transactions as snoopable (global).
– Regions can reside at any aligned location in the memory map.
– Byte-accessible ECC is protected using read-modify-write transaction accesses for
– Three inbound windows plus a configuration window on PCI and PCI Express
– Four outbound windows plus default translation for PCI and PCI Express
smaller-than-cache-line accesses.
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor