MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 47

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 47
Freescale Semiconductor
Local bus clock to output high impedance for LAD/LDP
Notes:
1. The symbols used for timing specifications follow the pattern of t
2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.
3. All signals are measured from BV
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
6. t
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
Local bus cycle time
Local bus duty cycle
LCLK[n] skew to LCLK[m] or LSYNC_OUT
Input setup to local bus clock (except LUPWAIT)
LUPWAIT input setup to local bus clock
Input hold from local bus clock (except LUPWAIT)
LUPWAIT input hold from local bus clock
LALE output transition to LAD/LDP output transition
(LATCH setup and hold time)
Local bus clock to output valid (except LAD/LDP and LALE)
Local bus clock to data valid for LAD/LDP
Local bus clock to address valid for LAD
Local bus clock to LALE assertion
Output hold from local bus clock (except LAD/LDP and
LALE)
Output hold from local bus clock for LAD/LDP
Local bus clock to output high Impedance (except
LAD/LDP and LALE)
inputs and t
timing (LB) for the input (I) to go invalid (X) with respect to the time the t
for clock one (1). Also, t
to the output (O) going invalid (X) or output hold time.
bypass mode to 0.4 × BV
through the component pin is less than or equal to the leakage current specification.
programmed with the LBCR[AHD] parameter.
complementary signals at BV
LBOTOT
describes the general timing parameters of the local bus interface at BV
is a measurement of the minimum time between the negation of LALE and any change in LAD. t
Table 46. Local Bus General Timing Parameters (BV
(First two letters of functional block)(reference)(state)(signal)(state)
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Table 47. Local Bus General Timing Parameters (BV
Parameter
Parameter
LBKHOX
DD
of the signal in question for 2.5-V signaling levels.
DD
symbolizes local bus timing (LB) for the t
/2.
DD
/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL
t
Symbol
Symbol
t
t
t
t
t
t
t
t
LBKH/
t
LBKSKEW
t
t
t
t
LBKHOZ2
t
LBKHOV1
LBKHOV2
LBKHOV3
LBKHOV4
LBKHOX1
LBKHOX2
LBKHOZ1
LBIVKH1
LBIVKH2
LBIXKH1
LBIXKH2
LBOTOT
t
LBK
(first two letters of functional block)(signal)(state)(reference)(state)
t
for outputs. For example, t
LBK
1
1
DD
LBK
LBK
= 2.5 V)
clock reference (K) goes high (H), in this case
clock reference (K) to go high (H), with respect
Min
Min
7.5
2.6
1.9
1.1
1.1
1.2
0.9
0.9
43
—
—
—
—
—
—
—
DD
—PLL Enabled (continued)
= 1.8 V DC)
LBIXKH1
Max
Max
150
2.6
3.2
3.2
3.2
3.2
2.6
12
57
—
—
—
—
—
—
—
DD
= 1.8 V DC.
symbolizes local bus
LBOTOT
Unit
Unit
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
is
Local Bus
Notes
Notes
3, 4
3, 4
3, 4
3, 4
—
—
for
5
2
7
6
3
3
3
3
3
5
47