MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 73

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

17 PCI Express
This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8544.
17.1
For more information, see
17.2
Table 58
17.3
The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm)
of each other at all times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance.
17.4
The following is a summary of the specifications for the physical layer of PCI Express on this device. For
further details as well as the specifications of the transport and data link layer please refer to the
PCI Express Base Specification. Rev. 1.0a.
Freescale Semiconductor
Notes:
1. Typical based on PCI Express Specification 2.0.
2. Guaranteed by characterization.
Symbol
t
t
REFCJ
REFPJ
t
REF
2
provides the AC requirements for the PCI Express SerDes clocks.
DC Requirements for PCI Express SD_REF_CLK and
SD_REF_CLK
AC Requirements for PCI Express SerDes Clocks
Clocking Dependencies
Physical Layer Specifications
REFCLK cycle time
REFCLK cycle-to-cycle jitter. Difference in the period of any
two adjacent REFCLK cycles
Phase jitter. Deviation in edge location with respect to
mean edge location
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Table 58. SD_REF_CLK and SD_REF_CLK AC Requirements
Parameter Description
Section 16.2, “SerDes Reference Clocks.”
Min
–50
—
—
Typ
10
—
—
Max
100
50
—
Units
ns
ps
ps
PCI Express
Notes
—
—
1
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