MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 23

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7.2
Table 20
8
This section provides the AC and DC electrical characteristics for enhanced three-speed and MII
management.
8.1
The electrical characteristics specified here apply to all gigabit media independent interface (GMII), 8-bit
FIFO interface (FIFO), serial gigabit media independent interface (SGMII), media independent interface
(MII), ten-bit interface (TBI), reduced gigabit media independent interface (RGMII), reduced ten-bit
interface (RTBI), and reduced media independent interface (RMII) signals except management data
input/output (MDIO) and management data clock (MDC). The 8-bit FIFO interface can operate at 3.3 or
2.5 V. The RGMII and RTBI interfaces are defined for 2.5 V, while the MII, GMII, TBI, and RMII
interfaces can be operated at 3.3 or 2.5 V. Whether the GMII, MII, or TBI interface is operated at 3.3 or
2.5 V, the timing is compliant with IEEE 802.3. The RGMII and RTBI interfaces follow the Reduced
Gigabit Media-Independent Interface (RGMII) Specification Version 1.3 (12/10/2000). The RMII
interface follows the RMII Consortium RMII Specification Version 1.2 (3/20/1998). The SGMII interfaces
follow the Serial Gigabit Media-Independent Interface (SGMII) Specification Version 1.8. The electrical
Freescale Semiconductor
Minimum baud rate
Maximum baud rate
Oversample rate
Notes:
1. CCB clock refers to the platform clock.
2. Actual attainable baud rate will be limited by the latency of interrupt processing.
3. The middle of a start bit is detected as the eighth sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values
Low-level output voltage (OV
Note:
1. Note that the symbol V
are sampled each sixteenth sample.
Enhanced Three-Speed Ethernet (eTSEC),
MII Management
provides the AC timing parameters for the DUART interface.
DUART AC Electrical Specifications
Enhanced Three-Speed Ethernet Controller (eTSEC)
(10/100/1000 Mbps)—SGMII/GMII/MII/TBI/RGMII/RTBI/RMII/FIFO
Electrical Characteristics
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Parameter
IN
, in this case, represents the OV
Table 19. DUART DC Electrical Characteristics (continued)
DD
Parameter
= min, I
Table 20. DUART AC Timing Specifications
OL
= 2 mA)
IN
Symbol
symbol referenced in
V
OL
Enhanced Three-Speed Ethernet (eTSEC), MII Management
Min
—
CCB clock/1,048,576
CCB clock/16
Table 1
Value
16
and
Max
0.4
Table
2.
baud
baud
Unit
Unit
—
V
Notes
Notes
—
1
2
3
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