MC68EC040FE25A Freescale Semiconductor, MC68EC040FE25A Datasheet - Page 209

• Manufacturer Part Number: MC68EC040FE25A
• Description: IC MPU 32BIT 25MHZ 184-CQFP
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68EC040FE25A

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Core Size: 32bit
• Program Memory Size: 8KB
• Cpu Speed: 25MHz
• Digital Ic Case Style: CQFP
• No. Of Pins: 184
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 184
• Package Type: CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

For processor resets after the initial power-on reset, RSTI should be asserted for at least
10 clock periods. Figure 7-45 illustrates timings associated with a reset when the
processor is executing bus cycles. Note that BB and TIP (and TA if driven during a
snooped access) are negated before transitioning to a three-state level.
Resetting the processor causes any bus cycle in progress to terminate as if TA or TEA
had been asserted. In addition, the processor initializes registers appropriately for a reset
exception. Section 8 Exception Processing describes exception processing. When a
RESET instruction is executed, the processor drives the reset out (RSTO) signal for 512
BCLK cycles. In this case, the processor resets the external devices of the system, and
the internal registers of the processor are unaffected. The external devices connected to
the RSTO signal are reset at the completion of the RESET instruction. An RSTI signal that
is asserted to the processor during execution of a RESET instruction immediately resets
the processor and causes the RSTO signal to negate. RSTO can be logically ANDed with
the external signal driving RSTI to derive a system reset signal that is asserted for both an
external processor reset and execution of a RESET instruction.
MOTOROLA
CDIS, MDIS,
IPL2–IPL0
SIGNALS
BCLK
RSTI
BUS
TIP
BG
BR
TS
BB
MI
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 7-45. Normal Reset Timing
CLOCKS
t 10
>
Go to: www.freescale.com
M68040 USER’S MANUAL
CLOCKS
2
CLOCKS
128
7- 67