MC68EC040FE25A Freescale Semiconductor, MC68EC040FE25A Datasheet - Page 57

• Manufacturer Part Number: MC68EC040FE25A
• Description: IC MPU 32BIT 25MHZ 184-CQFP
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68EC040FE25A

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Core Size: 32bit
• Program Memory Size: 8KB
• Cpu Speed: 25MHz
• Digital Ic Case Style: CQFP
• No. Of Pins: 184
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 184
• Package Type: CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

the logical addresses of the currently executing process. Portions of translation tables can
be dynamically allocated as the process requires additional memory.
The current privilege mode determines the use of the URP or SRP for translation of the
access. The root pointer contains the base address of the translation table’s root-level
table. The translation table consists of tables of descriptors. The table descriptors of the
root- and pointer-levels can be either resident or invalid. The page descriptors of the page-
level table can be resident, indirect, or invalid. A page descriptor defines the physical
address of a page frame in memory that corresponds to the logical address of a page. An
indirect descriptor, which contains a pointer to the actual page descriptor, can be used
when two or more logical addresses access a single page descriptor.
The table search uses logical addresses to access the translation tables. Figure 3-8
illustrates a logical address format, which is segmented into four fields: root index (RI),
pointer index (PI), page index (PGI), and page offset. The first three fields extracted from
the logical address index the base address for each table level. The seven bits of the
logical address RI field are multiplied by 4 or shifted to the left by two bits. This sum is
concatenated with the upper 23 bits of the appropriate root pointer (URP or SRP) to yield
the physical address of a root-level table descriptor. Each of the 128 root-level table
descriptors corresponds to a 32-Mbyte block of memory and points to the base of a
pointer-level table.
3-8
ROOT POINTER
Figure 3-7. Translation Table Structure
Freescale Semiconductor, Inc.
For More Information On This Product,
M68040 USER'S MANUAL
Go to: www.freescale.com
SECOND
LEVEL
LEVEL
THIRD
LEVEL
FIRST
ROOT
TABLES
POINTER
TABLES
PAGE
TABLES
MOTOROLA