MC68EC040FE25A Freescale Semiconductor, MC68EC040FE25A Datasheet - Page 99

• Manufacturer Part Number: MC68EC040FE25A
• Description: IC MPU 32BIT 25MHZ 184-CQFP
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68EC040FE25A

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Core Size: 32bit
• Program Memory Size: 8KB
• Cpu Speed: 25MHz
• Digital Ic Case Style: CQFP
• No. Of Pins: 184
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 184
• Package Type: CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

4.7.2 Data Cache
The IU uses the data cache to store operand data as it generates the data. The data
cache supports a line-based protocol allowing individual cache lines to be in one of three
states: invalid, valid, or dirty. To maintain coherency with memory, the data cache
supports both write-through and copyback modes, specified by the CM field for the page.
Read misses and write misses to copyback pages cause the cache controller to read a
new cache line from memory into the cache. If available, an invalid line in the selected set
is updated with the tag and data from memory. The line state then changes from invalid to
valid by setting the V-bit for the line. If all lines in the set are already valid or dirty, the
pseudo-random replacement algorithm is used to select one of the four lines and replace
the tag and data contents of the line with the new line information. Before replacement,
dirty lines are temporarily buffered and later copied back to memory after the new line has
been read from memory. If a snoop access occurs before the buffered line is written to
memory, the snoop controller snoops the buffer and the caches. Figure 4-6 illustrates the
three possible states for a data cache line, with the possible transitions caused by either
the processor or snooped accesses. Transitions are labeled with a capital letter, indicating
the previous state, followed by a number indicating the specific case listed in Table 4-4.
MOTOROLA
CPU Read Miss
CPU Read Hit
Cache Invalidate or Push
(CINV or CPUSH)
Alternate Master Read Hit
(Snoop Control = 01 — Leave Dirty)
Alternate Master Read Hit
(Snoop Control = 10 — Invalidate)
Alternate Master Write Hit
(Snoop Control = 01 — Leave Dirty or
Snoop Control = 10 — Invalidate)
Cache Operation
Table 4-3. Instruction-Cache Line State Transitions
Freescale Semiconductor, Inc.
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M68040 USER’S MANUAL
supply data to CPU and
update cache; go to valid
state.
Not Possible
No action; remain in
current state.
Not possible; not snooped.
Not Possible
Not Possible
Read line from memory;
Invalid Cases
Current State
V1
V2
V3
V4
V5
V6
Read line from memory; supply
data to CPU and update cache
(replacing old line); remain in
current state.
current state.
No action; go to invalid state.
Supply data to CPU; remain in
Not possible; not snooped.
No action; go to invalid state.
No action; go to invalid state.
Valid Cases
4- 15