MC68EC040FE25A Freescale Semiconductor, MC68EC040FE25A Datasheet - Page 239

• Manufacturer Part Number: MC68EC040FE25A
• Description: IC MPU 32BIT 25MHZ 184-CQFP
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68EC040FE25A

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Core Size: 32bit
• Program Memory Size: 8KB
• Cpu Speed: 25MHz
• Digital Ic Case Style: CQFP
• No. Of Pins: 184
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 184
• Package Type: CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

ATC—ATC Fault
LK—Locked Transfer (Read-Modify-Write)
RW—Read/Write
X—Undefined
SIZE—Transfer Size
TT—Transfer Type
TM—Transfer Modifier
8.4.6.3 WRITE-BACK STATUS. These fields contain status information for the three
possible write-backs that could be pending after the faulted access (see Figure 8-8). For a
data cache line-push fault or a MOVE16 write fault, WB1S is zero (invalid).
8.4.6.4 FAULT ADDRESS. The fault address (FA) is the initial address for the access that
faulted. The FA is a physical address only for cache pushes and a logical address for all
other cases. For a misaligned access that faults, the FA field contains the address of the
first byte of the transfer, regardless of which of the two or three bus transfers for the
misaligned access was faulted. For a push fault, the WB1A and FA addresses are the
same.
8.4.6.5 WRITE-BACK ADDRESS AND WRITE-BACK DATA. Write-back addresses
(WB3A, WB2A, and WB1A) are memory pointers that indicate where to place the write-
8-26
This bit is set for an ATC fault due to a nonresident entry (bus error during table search
or invalid descriptor encountered) or privilege violation (write protected or supervisor
only). It is cleared for a bus-errored instruction, data, or cache line-push access.
This bit is set if a fault occurred on a locked transfer; it is cleared otherwise.
This bit is set if a fault occurred on a read transfer; it is cleared otherwise.
The SIZE field corresponds to the original access size. If a data cache line read results
from a read miss and the line read encounters a bus error, the SIZE field in the resulting
stack frame indicates the size of the original read generated by the execution unit.
This field defines the TT1–TT0 signal encodings for the faulted transfer.
This field defines the TM2–TM0 signal encodings for the faulted transfer.
TM—Transfer Modifier
TT—Transfer Type
SIZE—Transfer Size
V—Valid Write (write-back pending if set)
Freescale Semiconductor, Inc.
7
V
Figure 8-8. Write-Back Status Format
For More Information On This Product,
6
SIZE
M68040 USER’S MANUAL
Go to: www.freescale.com
5
4
TT
3
2
TM
1
0
MOTOROLA