MC68EC040FE25A Freescale Semiconductor, MC68EC040FE25A Datasheet - Page 55

• Manufacturer Part Number: MC68EC040FE25A
• Description: IC MPU 32BIT 25MHZ 184-CQFP
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68EC040FE25A

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Core Size: 32bit
• Program Memory Size: 8KB
• Cpu Speed: 25MHz
• Digital Ic Case Style: CQFP
• No. Of Pins: 184
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 184
• Package Type: CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

CM—Cache Mode
W—Write Protect
3.1.4 MMU Status Register
The MMUSR is a 32-bit register that contains the status information returned by execution
of the PTEST instruction. The PTEST instruction searches the translation tables to
determine status information about the translation of a specified logical address. Transfers
to and from the MMUSR are long-word transfers. The fields of the MMUSR are defined
following Figure 3-6, which illustrates the MMUSR.
Physical Address
B—Bus Error
G—Global
U1, U0—User Page Attributes
3-6
31
This field selects the cache mode and access serialization as follows:
Section 4 Instruction and Data Caches provides detailed information on caching
modes, and Section 7 Bus Operation provides information on serialization.
This bit indicates if the transparent block is write protected. If set, write and read-modify-
write accesses are aborted as if the resident bit in a table descriptor were clear.
This 20-bit field contains the upper bits of the translated physical address. Merging
these bits with the lower bits of the logical address forms the actual physical address.
Bit 12 is undefined if a PTEST is executed with 8-Kbyte pages selected.
The B-bit is set if a transfer error is encountered during the table search for the PTEST
instruction. If the B-bit is set, all other bits are zero.
This bit is set if the G-bit is set in the page descriptor.
These bits are set if corresponding bits in the page descriptor are set.
00 = Cachable, Write-through
01 = Cachable, Copyback
10 = Noncachable, Serialized
11 = Noncachable
0 = Read and write accesses permitted
1 = Write accesses not permitted
PHYSICAL ADDRESS
Figure 3-6. MMU Status Register Format
Freescale Semiconductor, Inc.
For More Information On This Product,
M68040 USER'S MANUAL
Go to: www.freescale.com
12
11
B
10
G
U1 U 0
9
8
7
S
6
C M
5
M
4
O
3
MOTOROLA
W
2
1
T
R
0