MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 10

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MC68EC060RC66

Manufacturer Part Number
MC68EC060RC66
Description
IC MPU 32BIT 66MHZ 206-PGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MC68EC060RC66

Processor Type
M680x0 32-Bit
Speed
66MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
206-PGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Supply Voltage (max)
3.465V
Operating Supply Voltage (min)
3.135V
Operating Temp Range
0C to 110C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
206
Package Type
PGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Compliant
4.6.2
4.7
4.7.1
4.7.2
4.7.3
5.1
5.2
5.3
5.4
5.4.1
5.4.1.1
5.4.1.2
5.4.2
5.4.3
5.5
5.5.1
5.5.2
5.5.3
5.5.4
5.6
5.7
5.7.1
5.7.2
5.8
5.9
5.10
5.11
5.12
5.12.1
5.12.2
6.1
6.1.1
6.1.2
6.1.2.1
6.1.2.2
6.1.3
6.1.3.1
6.1.3.2
6.1.3.3
xii
Table of Contents
MMU Instructions........................................................................................ 4-30
Cache Operation........................................................................................... 5-1
Cache Control Register ................................................................................ 5-5
Cache Management ..................................................................................... 5-6
Caching Modes............................................................................................. 5-7
Cache Protocol ............................................................................................. 5-9
Cache Coherency ....................................................................................... 5-10
Memory Accesses for Cache Maintenance ................................................ 5-11
Push Buffer ................................................................................................. 5-13
Store Buffer................................................................................................. 5-13
Push Buffer and Store Buffer Bus Operation.............................................. 5-14
Branch Cache ............................................................................................. 5-14
Cache Operation Summary ........................................................................ 5-15
Floating-Point User Programming Model...................................................... 6-2
Effect of MDIS on Address Translation .................................................... 4-30
MOVEC .................................................................................................... 4-30
PFLUSH ................................................................................................... 4-30
PLPA ........................................................................................................ 4-30
Cachable Accesses .................................................................................... 5-7
Cache-Inhibited Accesses .......................................................................... 5-8
Special Accesses ....................................................................................... 5-9
Read Miss................................................................................................... 5-9
Write Miss ................................................................................................... 5-9
Read Hit...................................................................................................... 5-9
Write Hit.................................................................................................... 5-10
Cache Filling............................................................................................. 5-11
Cache Pushes .......................................................................................... 5-13
Instruction Cache...................................................................................... 5-15
Data Cache............................................................................................... 5-16
Floating-Point Data Registers (FP7–FP0) .................................................. 6-3
Floating-Point Control Register (FPCR) ..................................................... 6-3
Floating-Point Status Register (FPSR)....................................................... 6-4
Writethrough Mode ................................................................................... 5-7
Copyback Mode ....................................................................................... 5-8
Exception Enable Byte ............................................................................. 6-3
Mode Control Byte.................................................................................... 6-3
Floating-Point Condition Code Byte ......................................................... 6-5
Quotient Byte............................................................................................ 6-5
Exception Status Byte .............................................................................. 6-5
M68060 USER’S MANUAL
Floating-Point Unit
Section 5
Section 6
Caches
MOTOROLA

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