MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 18

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

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List of Illustrations
Floating-Point Condition Code (FPSR) .............................................................. 6-5
Floating-Point Quotient Byte (FPSR) ................................................................. 6-5
Floating-Point Exception Status Byte (FPSR).................................................... 6-6
Floating-Point Accrued Exception Byte (FPSR)................................................. 6-6
Intermediate Result Format.............................................................................. 6-12
Rounding Algorithm Flowchart ......................................................................... 6-14
Floating-Point State Frame .............................................................................. 6-35
Status Word Contents ...................................................................................... 6-36
Signal Relationships to Clocks........................................................................... 7-2
Full-Speed Clock................................................................................................ 7-2
Half-Speed Clock ............................................................................................... 7-2
Quarter-Speed Clock ......................................................................................... 7-3
Bus Control Register Format.............................................................................. 7-4
Internal Operand Representation....................................................................... 7-5
Data Multiplexing................................................................................................ 7-6
Byte Select Signal Generation and PAL Equation ............................................. 7-8
Example of a Misaligned Long-Word Transfer................................................. 7-10
Example of Misaligned Word Transfer ............................................................. 7-10
Misaligned Long-Word Read Bus Cycle Timing............................................... 7-11
Byte, Word, and Long-Word Read Cycle Flowchart ........................................ 7-13
Byte, Word, and Long-Word Read Bus Cycle Timing ...................................... 7-14
Line Read Cycle Flowchart .............................................................................. 7-17
Line Read Transfer Timing............................................................................... 7-18
Burst-Inhibited Line Read Cycle Flowchart ...................................................... 7-20
Burst-Inhibited Line Read Bus Cycle Timing.................................................... 7-21
Byte, Word, and Long-Word Write Transfer Flowchart .................................... 7-22
Long-Word Write Bus Cycle Timing ................................................................. 7-23
Line Write Cycle Flowchart .............................................................................. 7-26
Line Write Burst-Inhibited Cycle Flowchart ...................................................... 7-27
Line Write Bus Cycle Timing ............................................................................ 7-28
Locked Bus Cycle for TAS Instruction Timing.................................................. 7-30
Using CLA in a High-Speed DRAM Design ..................................................... 7-33
Interrupt Pending Procedure ............................................................................ 7-33
Assertion of IPEND .......................................................................................... 7-34
Interrupt Acknowledge Cycle Flowchart........................................................... 7-36
Interrupt Acknowledge Bus Cycle Timing ........................................................ 7-37
Autovector Interrupt Acknowledge Bus Cycle Timing ...................................... 7-38
Breakpoint Interrupt Acknowledge Cycle Flowchart......................................... 7-39
Breakpoint Interrupt Acknowledge Bus Cycle Timing ...................................... 7-40
LPSTOP Broadcast Cycle Flowchart ............................................................... 7-41
LPSTOP Broadcast Bus Cycle Timing, BG Negated ....................................... 7-42
LPSTOP Broadcast Bus Cycle Timing, BG Asserted ...................................... 7-43
Exiting LPSTOP Mode Flowchart..................................................................... 7-44
Exiting LPSTOP Mode Timing Diagram........................................................... 7-45
Word Write Access Bus Cycle Terminated with TEA Timing ........................... 7-48
M68060 USER’S MANUAL
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