MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 75

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Memory Management Unit
4.1.3 Transparent Translation Registers
The data transparent translation registers (DTTR0 and DTTR1) and instruction transparent
translation registers (ITTR0 and ITTR1) are 32-bit registers that define blocks of logical
address space that are untranslated by the MMU (the logical address is the physical
address). The TTRs operate independently of the E-bit in the TCR and the state of the MDIS
signal. Data transfers to and from these registers are long-word transfers. The TTR fields
are defined following Figure 4-5, which illustrates TTR format. Bits 12–10, 7, 4, 3, 1, and 0
always read as zero.
Bits 31–24—Logical Address Base
Bits 23–16—Logical Address Mask
E—Enable
S—Supervisor Mode
U0, U1—User Page Attributes
4-6
31
This 8-bit field is compared with address bits A31–A24. Addresses that match in this com-
parison (and are otherwise eligible) are transparently translated.
Since this 8-bit field contains a mask for the Logical Address Mask field, setting a bit in
this field causes the corresponding bit in the Logical Address Base field to be ignored.
Blocks of memory larger than 16 Mbytes can be transparently translated by setting some
of the logical address mask bits to ones. The low-order bits of this field can be set to define
contiguous blocks larger than 16 Mbytes. The mask can be used to define multiple non-
contiguous blocks of addresses.
This bit enables or disables transparent translation of the block defined by this register:
This field specifies the way FC2 is used in matching an address:
The user defines these bits, and the MC68060 does not interpret them. U0 and U1 are
echoed to the UPA0 and UPA1 signals, respectively, if an external bus transfer results
LOGICAL ADDRESS BASE
0 = Transparent translation disabled
1 = Transparent translation enabled
00 = Match only if FC2 = 0 (user mode access)
01 = Match only if FC2 = 1 (supervisor mode access)
1 X = Ignore FC2 when matching
Figure 4-5. Transparent Translation Register Format
24 23
LOGICAL ADDRESS MASK
M68060 USER’S MANUAL
16 15 14 13 12 11 10
E S-FIELD 0
0
0
U1 U0
9
8
7
0
6
CM
5
4
0
MOTOROLA
3
0
W
2
1
0
0
0