MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 319

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

1
MOTOROLA
Add 2(1/0) cycles to the (bd,An,Xi*SF) time for a memory indirect address.
Source<SFC> -> Rn
Rn -> Dest <DFC>
MOVES Function
ANDI to CCR
CHK
“
CINVA
CINVL
CINVP
CPUSHA
CPUSHL
CPUSHP
EORI to CCR
EXG
EXT
“
EXTB
LINK
“
LPSTOP
MOVE from CCR
MOVE to CCR
MOVE from USP
MOVE to USP
MOVEC (SFC,DFC,
USP,VBR,PCR)
MOVEC (CACR,TC,
TTR,BUSCR,URP,SRP)
NOP
ORI to CCR
PACK
“
“
1
Table 10-22. Status Register (SR) Instruction Execution Times
For these instructions, add the effective address calculation time.
Instruction
Table 10-24. Miscellaneous Instruction Execution Times
Byte, Word 1(1/0) 1(1/0) 1(1/0)
Byte, Word 1(0/1) 1(0/1) 1(0/1)
MOVE from SR
Long
Long
Size
MOVE to SR
Instruction
ANDI to SR
EORI to SR
ORI to SR
Table 10-23. MOVES Execution Times
Word
Word
Word
Word
Word
Word
1(1/0) 1(1/0) 1(1/0)
1(0/1) 1(0/1) 1(0/1)
Long
Long
Long
Long
Long
Long
Long
Long
Long
Size
Byte
Byte
Byte
(An) (An)+ –(An) (d16,An)
—
—
—
—
—
—
—
—
M68060 USER’S MANUAL
Register
15(0/1)
2(0/0)
2(0/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
2(0/1)
2(0/1)
9(0/0)
1(0/0)
2(0/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
2(0/0)
—
—
—
—
—
—
—
—
<=5394(0/512)
<=2838(0/256)
<=274(0/0)
<=26(0/1)
<=17(0/0)
<=18(0/0)
Memory
2(1/0)
2(1/0)
1(1/0)
1(0/1)
1(1/0)
1(0/1)
1(0/1)
1(1/0)
2(1/1)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Destination
1
1
1
1
2
Execution Time
(d8,An,Xi SF)
2
2
12(1/0)
2(1/0)
2(1/0)
2(0/1)
2(0/1)
12(0/0)
12(0/0)
1(0/1)
5(0/0)
Reg -> Dest
12(0/0)
15(0/0)
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
Instruction Execution Timing
(bd,An,Xi SF)
Source -> Reg
3(1/0)
3(0/1)
3(1/0)
3(0/1)
11(0/0)
14(0/0)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
(xxx).WL
2(1/0)
2(0/1)
2(1/0)
2(0/1)
10-23