MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 58

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Signal Description
The MC68060 provides the BB signal and protocol to provide compatibility with MC68040-
style buses. Either the BTT signal and protocol or the BB signal and protocol (but not both)
should be used. The unused signal, either BTT or BB, must be pulled up with a pullup resis-
tor and tied to V
. Use of the BTT signal and protocol yields higher performance at full bus
CC
speed and high operating frequencies. The use of BB and its associated protocol is not rec-
ommended at full bus speeds. The BTT protocol is discussed in detail in Section 7 Bus Op-
eration .
2.7.5 Bus Busy (BB)
This three-state bidirectional signal indicates that the bus is currently owned. BB is moni-
tored as a processor input to determine when an alternate bus master has released control
of the bus. The MC68060 samples bus availability on each clock-enabled clock edge. BG
must be asserted and both TS and BB must be negated (indicating the bus is free) before
the MC68060 asserts BB (with the first assertion of TS) as an output to assume ownership
of the bus. The processor keeps BB asserted until the external arbiter negates BG and the
processor completes the bus cycle in progress. When releasing the bus, the processor
negates BB for one clock period, then places it in a high-impedance state and begins to
sample it as an input. Note that the one clock period in which BB is negated is one MC68060
processor clock period, not a full clock-enabled clock period.
The MC68060 provides the BB signal and protocol to support compatibility with MC68040-
style buses. Either the BTT signal and protocol or the BB signal and protocol (but not both)
should be used. The unused signal, either BTT or BB, must be pulled up through a pullup
resistor and tied to V
. Use of the BTT signal and protocol yields higher performance at full
CC
bus speed and high operating frequencies. The use of BB and its associated protocol is not
recommended at full bus speeds. The BTT protocol is discussed in detail in Section 7 Bus
Operation.
2.8 PROCESSOR CONTROL SIGNALS
The following signals control the caches and MMUs and support processor and external
device initialization.
CDIS
2.8.1 Cache Disable (
)
When asserted, this input signal dynamically disables the on-chip caches on the next inter-
nal cache access boundary. The caches are enabled on the next boundary after CDIS is
negated.
CDIS does not flush the data and instruction caches. Cache entries remain unaltered and
become available after CDIS is negated, unless one of the cache invalidate instructions
(CINVA, CINVP, CINVL) are executed. The execution of one of the cache invalidate instruc-
tions may invalidate entries even if the caches have been disabled with this signal. The
assertion of CDIS does not affect snooping.
Refer to Section 5 Caches for information about the caches.
2-12
M68060 USER’S MANUAL
MOTOROLA