MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 77

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Memory Management Unit
descriptor, can be used when two or more logical addresses access a single page descrip-
tor.
The table search uses logical addresses to access the translation tables. Figure 4-7 illus-
trates a logical address format, which is segmented into four fields: root index (RI), pointer
index (PI), page index (PGI), and page offset. The first three fields extracted from the logical
address index the base address for each table level. The seven bits of the logical address
RI field are multiplied by 4 or shifted to the left by two bits. This sum is concatenated with
the upper 23 bits of the appropriate root pointer (URP or SRP) to yield the physical address
of a root-level table descriptor. Each of the 128 root-level table descriptors corresponds to
a 32-Mbyte block of memory and points to the base of a pointer-level table.
The seven bits of a logical address PI field are multiplied by 4 (shifted to the left by two bits)
and concatenated with the fetched root-level descriptor’s upper 23 bits to produce the phys-
ical address of the pointer-level table descriptor. Each of the 128 pointer-level table descrip-
tors corresponds to a 256-Kbyte block of memory.
4-8
31
ROOT INDEX FIELD
7 BITS
(RI)
ROOT POINTER
25 24
Figure 4-6. Translation Table Structure
POINTER INDEX FIELD
Figure 4-7. Logical Address Format
7 BITS
(PI)
M68060 USER’S MANUAL
18 17
PAGE INDEX FIELD
8K PAGE
4K PAGE
(PGI)
13 12 11
SECOND
LEVEL
THIRD
LEVEL
FIRST
LEVEL
13 BITS - 8K PAGE
12 BITS - 4K PAGE
PAGE OFFSET
ROOT
TABLES
POINTER
TABLES
PAGE
TABLES
MOTOROLA
0