MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 116

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

5.12.2 Data Cache
The integer unit uses the data cache to store operand data as it requires or generates the
data. The data cache supports a line-based protocol allowing individual cache lines to be in
one of three states: invalid, valid, or dirty. To maintain coherency with memory, the data
cache supports both writethrough and copyback modes, specified by the CM field for the
page.
MOTOROLA
Alternate Master Snoop Miss I5 Not possible.
TCI Asserted on Read Miss
Alternate Master Snoop Hit
Cache Invalidate or Push
(during the First Access)
Cache Operation
(CINV or CPUSH)
(Read or Write)
IPU Read Miss
IPU Read Hit
Table 5-2. Instruction Cache Line State Transitions
Figure 5-6. Instruction Cache Line State Diagram
I3—CINV/CPUSH
I6—TCI ASSERTED
INVALID
I3 No action; remain in current state.
I4 Not possible.
I6 Read line for memory; Supply data to
I1 Read line from memory; supply data to
I2 Not Possible.
IPU and update cache; go to valid state. V1
the IPU; remain in current state.
M68060 USER’S MANUAL
Invalid Cases
V4—SNOOP READ/WRITE HIT
I1—IPU READ MISS
V3—CINV/CPUSH
Current State
V4 No action; go to invalid state.
V6 Not Possible.
V2 Suppply data to IPU; remain in current
V3 No action; go to invalid state.
V5 No action; remain in current state.
V1—IPU READ MISS
V2—IPU READ HIT
V5—SNOOP MISS
Read line from memory; supply data to
IPU and update cache (replacing old
line); remain in current state.
state.
VALID
Valid Cases
Caches
5-17