MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 89

• Manufacturer Part Number: MC68EC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Memory Management Unit
updated before the MC68060 allows a page to be accessed. Table 4-1 lists the page
descriptor update operations for each combination of U-bit, M-bit, write-protected, and read
or write access type.
An alternate address space access is a special case that is immediately used as a physical
address without translation. Because the MC68060 implements a merged instruction and
data space, instruction address spaces (SFC/DFC = $6 or $2) using the MOVES instruction
are converted into data references (SFC/DFC = $5 or $1). The data memory unit handles
these translated accesses as normal data accesses. If the access fails due to an ATC fault
or a physical bus error, the resulting access error stack frame contains the converted func-
tion code in the TM field for the faulted access. If the MOVES instruction is used to write
instruction address space, then to maintain cache coherency, the corresponding addresses
must be invalidated in the instruction cache. The SFC and DFC values and results for nor-
mal (TT = 0) and for MOVES (TT = 10) accesses are listed in Table 4-2.
4.2.6 Address Translation Protection
The MC68060 MMUs provide separate translation tables for supervisor and user address
spaces. The translation tables contain both mapping and protection information. Each table
and page descriptor includes a write-protect (W) bit that can be set to provide write protec-
4-20
NOTE: WP indicates the accumulated write-protect status.
Previous Status
U-Bit
0
0
1
1
0
0
1
1
0
0
1
1
Table 4-1. Updating U-Bit and M-Bit for Page Descriptors
M-Bit
0
1
0
1
0
1
0
1
0
1
0
1
SFC/DFC Value
WP Bit
X
0
1
Table 4-2. SFC and DFC Values
000
001
010
011
100
101
110
111
Access
M68060 USER’S MANUAL
Type
Read
Write
Locked RMW Access to Set U
Locked RMW Access to Set U
None
None
Write to Set U and M
Write to Set U
Write to Set M
None
None
None
None
None
TT
10
00
00
10
10
00
00
10
Update Operation
Page Descriptor
Results
000
001
001
011
100
101
101
111
TM
U-Bit
New Status
1
1
1
0
0
1
1
1
1
1
1
1
M-Bit
0
1
1
0
1
0
1
0
1
1
1
1
MOTOROLA